NAND Flash Subdivision Layout for Host-Managed Multi-Plane Access
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Solution Overview
Problem
Conventional NAND flash memory systems face challenges in realizing the benefits of multi-plane and multi-die architectures due to limitations in logical-to-physical address translation, leading to inefficient data access and increased latency, particularly in systems with random access patterns.
Innovation Solution
A memory controller and host collaboration mechanism that provides the host with information about memory geometry and multi-plane capabilities, allowing it to directly manage physical address assignments and issue commands that align with device addressing restrictions, thereby facilitating efficient multi-plane and multi-die data storage and access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional logical-to-physical address translation is used in multi-plane memory systems, then the memory controller can manage address mapping automatically, but latency increases and bus utilization decreases due to translation overhead and sequential access patterns
Solution Approach 1:
The host system performs preliminary actions by directly managing physical address assignments and issuing multi-plane commands before data access operations. The host pre-configures address mappings and issues coordinated multi-plane commands to multiple memory devices simultaneously, eliminating the need for real-time translation during data access and reducing latency.
Solution Approach 2:
The patent extracts the address translation function from the memory controller and relocates it to the host system. The memory controller is relieved of translation overhead, allowing it to focus on command execution, while the host directly manages physical address assignments and issues optimized multi-plane commands to reduce access latency.
2Quantity of substance
If multi-plane access is implemented with common IO and address circuitry, then memory capacity is increased, but access efficiency decreases due to addressing and timing restrictions
Solution Approach 1:
The patent segments the memory system into multiple independent memory devices, each with its own IO and address circuitry. The host issues separate commands to each device, allowing parallel access without the timing restrictions of shared circuitry. This segmentation enables true multi-plane access while maintaining high access efficiency.
Solution Approach 2:
The patent transitions from a two-dimensional plane structure with shared circuitry to a multi-dimensional architecture where multiple devices are accessed in parallel through independent circuit paths. This adds a temporal dimension to the access pattern, allowing simultaneous operations across multiple devices without interfering with each other.
3Device complexity
If sequential logical addresses are assigned by memory controller, then address management is simplified, but data access efficiency decreases due to scattered physical locations and inability to group related data for multi-plane access
Solution Approach 1:
The patent inverts the traditional address management approach by having the host system directly manage physical address assignments instead of the memory controller. The host assigns physical addresses in a manner that groups related data across multiple devices, enabling efficient multi-plane access while maintaining simplified address management through direct host control.
Data Source
AI summary
This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.