NAND Flash CMOS Integration for Low-Latency In-Storage DSP
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional digital signal processing (DSP) tasks on large data sets require significant host system resources, leading to resource unavailability for extended periods and inefficient execution within data storage devices.
Innovation Solution
Implementing CMOS structures coupled to non-volatile memory (NVM) die within data storage devices to perform atomic calculations, with results aggregated by a controller and back-propagated or forwarded to the host system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If DSP calculations are performed on the host system, then computation capability is sufficient, but host system resources become unavailable for extended periods
Solution Approach 1:
The patent divides the DSP computation task into multiple atomic calculation components and distributes them across multiple independent CMOS structures coupled to different NVM dies. Each CMOS structure processes a portion of the calculation independently, enabling parallel execution and preventing host system resource exhaustion.
2Productivity
If DSP calculations are performed within the data storage device, then resource availability improves, but computation capability must be enhanced
Solution Approach 1:
The patent configures CMOS structures coupled to NVM dies to perform both traditional memory functions and DSP calculation functions. The same hardware infrastructure (CMOS-NVM integration) serves dual purposes: data storage and parallel computation, eliminating the need for separate dedicated computation resources.
3Ease of operation
If data is transferred between storage and processing units, then computation can be performed, but latency increases due to intermediate data transfers
Solution Approach 1:
The patent merges the storage function (NVM die) and processing function (CMOS structure) into a tightly integrated unit. The CMOS structure is directly coupled to the NVM die, allowing calculations to be performed on data without intermediate transfers to separate processing units, thereby eliminating transfer latency.
Data Source
AI summary
A method and apparatus for systems and methods for digital signal processing (DSP) in a non-volatile memory (NVM) device comprising CMOS coupled to NVM die, of a data storage device. According to certain embodiments, one or more DSP calculations are provided by a controller to the CMOS components of the NVM, that configure one or more memory die to carry out atomic calculations on the data resident on the die. The results of calculations of each die are provided to an output latch for each die, back-propagating data back to the configured calculation portion as needed, otherwise forwarding the results to the controller. The controller aggregates the results of DSP calculations of each die and presents the results to the host system.