NAND Flash Memory Inhibiting Word Line Voltage Control
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Solution Overview
Problem
Conventional NAND-type non-volatile memory devices face reliability issues due to channel boosting voltage, which damages memory transistors and affects programming and reading operations, leading to decreased program windows and short-channel effects.
Innovation Solution
A method for operating NAND-type non-volatile memory devices involves applying an inhibiting voltage to specific word lines and a programming voltage to selected lines, preventing data programming on unselected bit lines without using high channel boosting voltages, thereby reducing transistor damage and enhancing operational reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If channel boosting voltage is applied to prevent data programming on unselected bit lines, then programming selectivity is improved, but memory transistor reliability deteriorates due to hot carrier damage and GIDL effects
Solution Approach 1:
The patent introduces an intermediary mechanism (inhibiting word line with inhibiting voltage) between the programming operation and the unselected memory transistors. Instead of directly applying high channel boosting voltage to unselected bit lines, the invention uses the inhibiting word line as a mediator to prevent programming indirectly, thereby avoiding hot carrier damage while maintaining programming selectivity
Solution Approach 2:
The patent changes the voltage parameter application strategy by applying inhibiting voltage to word lines instead of channel boosting voltage to bit lines. This parameter change transforms the approach from direct high-voltage application to a controlled voltage distribution method that achieves the same selectivity goal without the harmful side effects
2Manufacturing precision
If high channel boosting voltage is applied to unselected bit lines, then data programming prevention is improved, but program and pass windows decrease due to transistor damage
Solution Approach 1:
The inhibiting word line serves as an intermediary that prevents data programming on unselected bit lines without requiring high channel boosting voltages. This intermediary approach maintains adequate program and pass windows by avoiding direct high-voltage stress on the memory transistors
3Measurement precision
If channel boosting technique is used to achieve selective programming, then programming accuracy is improved, but operational reliability deteriorates due to short-channel effects
Solution Approach 1:
The patent changes the voltage application parameters from high channel boosting voltage on bit lines to controlled inhibiting voltage on word lines. This parameter change maintains programming accuracy while avoiding the short-channel effects that occur with high voltage application to unselected transistors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents data programming on unselected memory transistors without channel boosting, reducing transistor damage and maintaining program windows, thus improving the operational reliability and reducing power consumption of non-volatile memory devices.
Implementation Method 1
An inhibiting voltage is applied to at least one inhibiting word line including a word line closest (nearest) to a string selection line
Implementation Method 2
A programming voltage is applied to a selected word line
Implementation Method 3
memory transistors coupled with the selected bit line may be electrically connected to each another by an electrical field effect source/drain induced by a fringe field
Data Source
AI summary
A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile memory device are provided. A selected bit line for programming and unselected bit lines for preventing programming are determined from the plurality of bit lines. An inhibiting voltage is applied to at least one inhibiting word line chosen from the plurality of word lines. The at least one inhibiting word line includes a word line positioned closest to a string selection line. A programming voltage is applied to a selected word line chosen from the plurality of word lines. Data is programmed into a memory transistor coupled with the selected word line and the selected bit line while preventing data from being programming into memory transistors coupled with the unselected bit line.