NAND Flash Page Programming With Integrated ECC and Block Data

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Solution Overview

Problem

Multi-level cell (MLC) NAND flash memory devices experience increased error rates due to higher memory density, requiring an efficient error correction scheme to maintain data integrity, which existing technologies have not adequately addressed.

Innovation Solution

The implementation of an error correction system that integrates error correction code (ECC) data with memory operations, utilizing ECC check bits and block management data to correct errors during programming and read operations, and employing ECC techniques such as Hamming, BCH, or Reed-Solomon codes to ensure data accuracy in MLC NAND flash memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multi-level cell (MLC) configuration is used to increase memory density, then storage capacity is improved, but error rates increase

Engineering Contradiction:
Improvememory densityVSAvoiderror rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent divides the error correction process into multiple independent sectors, where each sector can be corrected separately. This segmentation allows the ECC system to handle errors in specific regions without affecting the entire data structure, thereby maintaining reliability while supporting high-density MLC storage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent incorporates error correction code (ECC) data and block management data into the memory structure during the programming phase. By preparing and integrating these correction codes in advance, the system enables automatic error detection and correction during subsequent read operations, preventing errors from compromising data integrity in high-density MLC cells.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If error correction code (ECC) data is integrated with block management data, then data integrity is improved, but device complexity increases

Engineering Contradiction:
Improvedata integrityVSAvoiddata structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges ECC data and block management data into a unified integrated structure within the memory device. This combination allows both error correction functionality and block management operations to share the same data storage resources, reducing the need for separate dedicated structures and thereby managing complexity while enhancing data integrity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The integrated data structure serves multiple functions simultaneously: it stores error correction codes, block management information, and data integrity verification data. This multi-functionality reduces the overall complexity by eliminating redundant separate structures, as a single integrated structure performs multiple critical roles in maintaining data reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If efficient error correction scheme is implemented, then reliability is improved, but time and resources for correction operations increase

Engineering Contradiction:
Improveerror correction efficiencyVSAvoidcorrection operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements a self-service error correction mechanism where the memory device automatically detects and corrects errors using integrated ECC data without requiring external intervention. The system autonomously performs syndrome calculation, error location, and correction operations, minimizing the time and computational resources needed compared to manual or external correction methods.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent replaces complex mechanical or sequential correction processes with parallel computational operations. By using hardware-based ECC engines that perform error detection and correction through parallel processing rather than sequential steps, the system reduces correction operation time and resource consumption while maintaining high reliability.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20110093766A1Programming management data for a memory
Publication Date: 2011.04.21 MICRON TECHNOLOGY INC
  • US20110093766A1 patent drawing
  • US20110093766A1 patent drawing
  • US20110093766A1 patent drawing

AI summary

Methods, apparatus, systems, and data structures may operate to combine block management data with a portion of data, to generate error correction data for the combined portion, and to store the data, the block management data, the error correction data for the combined portion, and error correction data for the data in a memory. Methods, apparatus, systems, and data structures may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and combine block management data with the particular sector to generate a modified sector. Additionally, various methods, apparatus, systems, and data structures may operate to generate or store error correction data for the modified sector and combine the plurality of sectors, the error correction data for each of the plurality of sectors other than the particular page, and the block management data and the error correction data for the modified sector.