NAND Flash Memory Drive Circuit Voltage Control for Inter-Cell Interference
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Solution Overview
Problem
NAND-type flash memory devices face issues during erase verification operations due to inter-cell interference, where threshold voltages of memory cells at the ends of the memory string appear different from actual values, leading to insufficient or over-erase states.
Innovation Solution
The implementation of a nonvolatile semiconductor storage device with a cell array structure that includes selection and dummy wires, where the voltage applied to the dummy wire is controlled to create a voltage difference that aligns the effective threshold voltages of all memory cells during erase verification, ensuring uniformity and preventing false data writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If erase verification operation is performed in NAND-type flash memory, then data storage state can be verified, but inter-cell interference causes threshold voltage to appear different from actual value
Solution Approach 1:
A dummy cell is introduced as an intermediary element between the memory cell and the selection transistor. This dummy cell absorbs the inter-cell interference effect by being subjected to the same interference conditions, allowing the actual memory cell's threshold voltage to be measured accurately without the harmful interference effects
Solution Approach 2:
The patent changes the electrical parameters (voltage levels) applied to the dummy cell and memory cell during erase verification to compensate for inter-cell interference. By adjusting these parameters, the effective threshold voltage measurement reflects the actual threshold voltage rather than the apparent value distorted by interference
2Quantity of substance
If memory cell size is reduced to achieve high density integration, then storage capacity increases, but inter-cell interference effect becomes more significant
Solution Approach 1:
The dummy cell serves as a mediator that experiences the same inter-cell interference conditions as the memory cells, allowing the system to compensate for interference effects even as cell density increases and interference becomes more significant
Solution Approach 2:
The patent applies different voltage conditions to different cells based on their location and function. The dummy cell is subjected to specific voltage conditions that account for its position and the interference it experiences, while memory cells receive adjusted voltages to compensate for their specific interference environments
3Ease of operation
If uniform voltage is applied to all cells during erase operation, then operation is simple, but threshold voltage uniformity across all cells is not achieved
Solution Approach 1:
Different voltage levels are applied to different cells based on their specific positions and interference conditions. The dummy cell receives a voltage that accounts for its specific interference environment, while memory cells receive adjusted voltages to achieve uniform threshold voltage across all cells despite their different local conditions
Data Source
AI summary
A nonvolatile semiconductor storage device according to an embodiment includes a drive circuit. A voltage applied to a dummy wire connected to a first dummy cell adjacent to a memory string is defined as a first dummy wire voltage, a voltage applied to a selection wire connected to a first memory cell adjacent to the first dummy cell is defined as a first selection wire voltage, and a voltage applied to a selection wire connected to a second memory cell adjacent to the first memory cell is defined as a second selection wire voltage. When the second selection wire voltage is lower than the first dummy wire voltage in an erase operation, the drive circuit controls voltages so that a difference between the first dummy wire voltage and the second selection wire voltage is less than a difference between the first dummy wire voltage and the first selection wire voltage.