NAND Flash Page Inversion Seeds for Uniform Program-Erase Wear
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Solution Overview
Problem
NAND flash memory devices experience uneven wear out due to non-uniform NAND cell state transitions during program-erase cycles, leading to accelerated degradation and increased susceptibility to read and program disturb errors.
Innovation Solution
Implementing a multi-bit inversion seed and circular shift flip sequence for each page type in non-volatile memory devices to ensure uniform randomness in NAND cell state transitions, using a joint hardware and firmware design that includes a system-on-chip (SoC) for fast data inversion operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If traditional write operations are used without uniform randomness, then write speed is maintained, but uneven wear out occurs leading to accelerated degradation and reduced memory lifespan
Solution Approach 1:
The patent applies bit inversion operations where data bits are flipped based on inversion seeds. This inversion mechanism transforms the data pattern before writing, ensuring that even identical data writes result in different physical states in the memory cells, thereby distributing wear uniformly across all cells regardless of the original data pattern.
Solution Approach 2:
The patent changes the state parameters of data bits through inversion operations. By modifying bit values based on inversion seeds that change with each program-erase cycle, the physical state transitions of memory cells are randomized, preventing any specific cell from experiencing excessive stress and extending overall memory lifespan.
2Reliability
If wear leveling techniques are employed to distribute write operations, then wear uniformity is improved, but additional complexity is introduced in managing write operations
Solution Approach 1:
The inversion seed mechanism automatically generates different inversion patterns for each program-erase cycle without requiring external wear leveling management. The system self-regulates wear distribution through the automatic application of inversion operations based on cycle-count-dependent seeds, eliminating the need for complex wear leveling algorithms and their associated management overhead.
3Duration of action of stationary object
If multi-bit inversion seeds with circular shift flip sequences are implemented, then wear uniformity and memory lifespan are extended, but processing complexity increases
Solution Approach 1:
The inversion seeds and circular shift flip sequences are pre-computed and stored in lookup tables before actual data writing occurs. This preliminary preparation allows the complex inversion operations to be executed efficiently during write operations by simply retrieving and applying pre-computed sequences, reducing real-time processing complexity while maintaining wear uniformity benefits.
Data Source
AI summary
Devices, systems, and methods for improving performance of a non-volatile memory are described. An example method includes generating, based on a number of program erase cycles of the non-volatile memory, an inversion seed for a page type of the non-volatile memory, and then generating a circular shift flip sequence based on the inversion seed and a flip sequence. The method further includes performing a bit-flipping operation on an input bit sequence based on the circular shift flip sequence to generate an intermediate bit sequence, processing the intermediate bit sequence to generate an output bit sequence, and finally, writing the output bit sequence to a page in the non-volatile memory. In this example, the page that the output bit sequence is written (or programmed) to is of the page type for which the inversion seed and circular shift flip sequence are generated.