NAND Flash Read Circuit Using Word-Line Kick and Split Gate Bias
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Solution Overview
Problem
Existing NAND type flash memory devices face challenges in efficiently reading data from memory cells due to variations in threshold voltage distributions, leading to inaccuracies in data interpretation.
Innovation Solution
The semiconductor memory device employs a kick operation where a kick voltage higher than the read voltage is applied to the word line before the read voltage, and different gate voltages are applied to transistors in the sense amplifiers to enhance data reading accuracy by controlling current flow through bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a kick operation is performed on both control signals BLC1 and BLC2, then data reading speed is improved, but bit line overcharge or overload occurs causing read errors
Solution Approach 1:
The patent applies different kick operation strategies to different sense amplifier segments based on their specific characteristics. The control signal generation unit selectively performs kick operations on control signals (BLC1 for near-side segments, BLC2 for far-side segments) based on the address of the selected block, optimizing each segment's performance while avoiding overcharge or overload issues in specific segments.
Solution Approach 2:
The sense amplifier module is divided into multiple sense amplifier segments (first sense amplifier segment and second sense amplifier segment) with different characteristics. The patent manages kick operations separately for each segment by controlling different control signals (BLC1 and BLC2), allowing optimized performance for each segment without causing overcharge or overload in any single segment.
2Reliability
If different kick operations are applied to near-side and far-side sense amplifier segments, then read errors are reduced, but device complexity increases
Solution Approach 1:
The control signal generation unit is designed to generate multiple control signals (BLC1 and BLC2) that can be selectively applied to different sense amplifier segments. This multi-functional control mechanism allows the same unit to manage kick operations for both near-side and far-side segments, reducing overall device complexity while maintaining optimized performance for each segment.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.