NAND Flash Latch Group Compression for Soft-Decision Reads
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Solution Overview
Problem
Traditional NAND flash memory devices face challenges in accurately reading data due to voltage discrimination as either 0 or 1, leading to performance issues and reduced lifespan.
Innovation Solution
Implementing soft decision technology to analyze voltage more finely and enhance error correction codes, along with a nonvolatile memory device design that includes separate address controllers for reading and writing compressed data, reducing the size of storage registers through sequential repetition of read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If soft decision technology is implemented to analyze voltage more finely, then data reading accuracy is improved, but device complexity increases
Solution Approach 1:
The patent divides the latch array into multiple latch groups (first latch group, second latch group, etc.) that can be independently controlled. This segmentation allows the system to process and compress data in manageable portions, reducing the complexity burden of soft decision technology while maintaining its accuracy benefits.
Solution Approach 2:
The patent introduces an encoder as an intermediary component that compresses data from the latch groups before storage. This encoder acts as a mediator that handles the complex compression task, allowing the latch groups to focus on data storage while the encoder manages the complexity of soft decision data processing.
2Quantity of substance
If data compression is implemented in the memory device, then storage capacity is optimized, but device complexity increases
Solution Approach 1:
The latch array is segmented into multiple independently controllable latch groups, allowing compression operations to be performed on specific groups without affecting others. This segmentation enables gradual implementation of compression, reducing the overall complexity impact while maximizing storage optimization.
Solution Approach 2:
The address controller is designed to perform multiple functions: it controls both read operations (output address) and write operations (input address) to the latch groups, and manages the compression process. This multi-functionality reduces the need for separate dedicated circuits, optimizing storage capacity while controlling complexity.
3Productivity
If separate address controllers are used for reading and writing, then data access efficiency is improved, but device complexity increases
Solution Approach 1:
The patent merges the address control functionality into a single address controller that handles both read and write operations. By combining these functions in one controller rather than using separate controllers, the system achieves efficient data access through unified management while avoiding the complexity increase that would result from multiple independent control units.
Data Source
AI summary
A nonvolatile memory device includes a plurality of latch groups, an address controller, an encoder, and a buffer. The address controller controls an input address and an output address to indicate one of the plurality of latch groups. The encoder receives sector data from a latch group corresponding to the output address among the plurality of latch groups and also compresses the received sector data. The buffer stores the compressed sector data. Among the plurality of latch groups, the compressed sector data stored in the buffer is overwritten in a latch group corresponding to the input address.