NAND Flash Latch Circuit Resetting for High-Speed Readout

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Solution Overview

Problem

In NAND flash memory, the continuous readout operation is constrained by the need to reset the latch circuit after data transmission, which can lead to insufficient time for resetting due to advanced start timings, affecting high-speed data output and latch circuit reliability.

Innovation Solution

The proposed solution involves a pre-charging step for the bit line and NAND string, followed by a resetting step that electrically connects the latch circuit to a reference potential during the discharging period, ensuring adequate time for latch circuit resetting between pre-charging and discharging operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the latch circuit resetting is performed after data transmission to another latch circuit, then the continuous readout speed is improved, but the resetting time becomes insufficient affecting reliability

Engineering Contradiction:

Improvecontinuous readout speedVSAvoidlatch circuit resetting reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The latch circuit resetting operation is performed in advance during the discharging period of the NAND string, before the actual data readout begins. This preliminary action ensures that the latch circuit is fully reset and ready to receive new data without compromising the continuous readout speed, as the resetting occurs in parallel with other operations that would otherwise occur sequentially

Inventive Principle:

Principle #10Preliminary action

2Reliability

If the latch circuit is reset during the discharging period of the NAND string, then the resetting time is sufficient, but the readout timing becomes constrained

Engineering Contradiction:

Improvelatch circuit resetting completenessVSAvoidreadout timing flexibility

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent establishes a periodic operation cycle where specific operations are performed during designated time periods: pre-charging during the first period, latch resetting during the discharging period, and data readout during subsequent periods. This periodic structure ensures that each operation has dedicated time for reliable execution while maintaining overall system productivity through systematic time management

Inventive Principle:

Principle #19Periodic action

3Reliability

If the pre-charging time is extended to ensure proper bit line charging, then the data retention reliability is improved, but the overall readout time increases

Engineering Contradiction:

Improvedata retention reliabilityVSAvoidreadout time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent maintains continuous useful action by overlapping operations that can occur simultaneously: the latch circuit resetting occurs during the NAND string discharging period, and the pre-charging of the bit line occurs during a separate time period. This continuous operation without idle waiting time ensures data retention reliability through proper charging while minimizing overall readout time through efficient time utilization

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS11775441B2Semiconductor apparatus and readout method

Publication Date: 2023.10.03 WINBOND ELECTRONICS CORP

AI summary

A semiconductor apparatus implementing a high speed data output and compensating a resetting of a latch circuit is provided. A readout method of a NAND type flash memory includes: a pre-charging step performing a pre-charging on a bit line and a NAND string connected to the bit line through a sense node (SNS); a resetting step performing a resetting on the latch circuit after the pre-charging; and a discharging step performing a discharging on the NAND string after the resetting.