3D Stacked NAND Flash Memory Array Layer Selection Optimization
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Solution Overview
Problem
Conventional 3D stacked NAND flash memory arrays face limitations in improving the degree of integrity due to the increased number of string selection lines (SSLs) required for layer selection, especially as the number of vertically stacked layers increases, leading to inefficiencies and waste in area utilization.
Innovation Solution
A 3D stacked NAND flash memory array with a multi-level operation method that minimizes the number of SSLs by using a configuration of active lines, word lines, and string selection lines with different threshold voltages, allowing for efficient layer selection through the use of string selection transistors and ground selection transistors, enabling more layers to be selected with fewer SSLs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of vertically stacked layers is increased to improve storage capacity, then the degree of integrity is improved, but the number of string selection lines (SSLs) required for layer selection increases, leading to area waste and reduced manufacturing efficiency
Solution Approach 1:
The patent transitions from a 2D planar structure to a 3D stacked structure, enabling vertical layering of memory cells. This dimensional change allows multiple layers to be stacked vertically, increasing storage capacity without proportionally increasing the number of SSLs, as the same SSL can serve multiple layers through the stacking architecture.
Solution Approach 2:
Each SSL is designed to serve multiple functions by controlling multiple layers simultaneously. The SSL structure enables it to select specific layers for read/write operations while maintaining control over other layers, reducing the total number of SSLs needed compared to having one SSL per layer.
2Adaptability or versatility
If more SSLs are used to select more layers, then layer selection capability is improved, but area utilization deteriorates due to the wider gate length requirement of SSLs
Solution Approach 1:
By stacking layers vertically in the third dimension, the patent enables more layers to be selected without proportionally increasing the horizontal area occupied by SSLs. The vertical stacking allows SSLs to extend through multiple layers, reducing the need for additional SSLs and improving area utilization.
Solution Approach 2:
The patent merges the function of multiple SSLs into a single SSL structure that can control multiple layers. By combining the layer selection functionality across stacked layers, the design reduces the total number of SSLs required, thereby improving area utilization while maintaining layer selection capability.
3Reliability
If the gate length of SSLs is increased to overcome leakage current and short channel effect, then device reliability is improved, but the number of SSLs required increases, worsening area efficiency
Solution Approach 1:
The vertical stacking architecture allows SSLs with longer gate lengths to control multiple layers, so that while each SSL maintains the necessary gate length for reliability, the total number of SSLs is reduced. This dimensional approach allows long-gate SSLs to serve multiple layers simultaneously.
Solution Approach 2:
Each SSL with its longer gate length is designed to control multiple layers, making it a universal control element. This multi-functionality reduces the total number of SSLs needed, thereby improving area efficiency while maintaining the reliability benefits of longer gate lengths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces the number of SSLs needed for layer selection, allowing for a higher degree of integrity and increased number of selectable layers compared to traditional methods, while maintaining efficient operation and minimizing area waste.
Implementation Method 1
insulating layers including a charge storage layer between each of the string selection lines and the semiconductor layers
Data Source
AI summary
This invention provides a 3D stacked NAND flash memory array and operation method thereof enabling to operate by LSM (a layer selection by multi-level operation) and to get rid of the waste of unnecessary areas by minimizing the number of SSLs needed for a layer selection though the number of layers vertically stacked is increased.