NAND Flash LDPC Decoding With Dual-Decoder Early Termination
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Solution Overview
Problem
Current error correction systems in NAND flash storage, particularly LDPC codes, face challenges in latency and processing performance due to iterative decoding processes that are not suitable for latency-sensitive or processing-intensive applications, as they often require a large number of iterations to correct errors effectively.
Innovation Solution
A data processing system with a dual-decoder architecture that includes a first decoder for normal decoding and a second decoder for fast decoding, allowing early termination of LDPC iterative decoding based on syndrome weight and iteration thresholds, reducing the number of iterations required for error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative LDPC decoding is performed to ensure error correction performance, then reliability is improved, but decoding latency and processing time increase
Solution Approach 1:
The patent applies partial action by performing only a subset of the required LDPC decoding iterations. Instead of completing all iterations to ensure full error correction performance, the system performs a limited number of iterations (e.g., 1-3 iterations) and terminates early. This partial execution reduces decoding latency significantly while maintaining acceptable error correction performance for latency-sensitive applications.
Solution Approach 2:
The patent implements dynamic decoding by making the number of iterations adjustable based on application requirements. The system can dynamically select between different iteration counts (e.g., 1 iteration for low-latency applications, 3 iterations for higher reliability needs) rather than using a fixed iteration count. This dynamic approach allows the system to adapt the decoding process to specific performance requirements.
2Reliability
If iterative LDPC decoding is performed to ensure error correction performance, then reliability is improved, but processing complexity and computational burden increase
Solution Approach 1:
The patent reduces processing complexity by performing only partial LDPC decoding iterations. By limiting the decoding process to 1-3 iterations instead of the full iterative process, the computational burden is significantly reduced. This partial execution makes the system more suitable for processing-intensive applications while maintaining adequate error correction capability.
3Speed
If early termination of LDPC decoding is implemented to reduce latency, then decoding speed is improved, but error correction performance may deteriorate
Solution Approach 1:
The patent carefully balances speed and reliability by performing a specific number of partial iterations (1-3 iterations) rather than terminating immediately. This controlled partial execution maintains sufficient error correction performance while achieving the desired latency reduction, avoiding complete termination that would sacrifice reliability.
Solution Approach 2:
The system dynamically adjusts the number of decoding iterations based on application-specific requirements. For latency-sensitive applications, fewer iterations (1-2) are performed to maximize speed. For applications requiring higher reliability, the system can perform more iterations (up to 3 or more). This dynamic adjustment allows the system to optimize the trade-off between speed and error correction performance for different use cases.
Data Source
AI summary
A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.