NAND Flash Memory Leak Current Control via Local Potential Wells
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Solution Overview
Problem
Conventional NAND flash memory devices face challenges in curbing leak current from non-selected memory strings during read operations, which affects bit density and memory capacity, and existing methods are insufficient in further reducing this leak current.
Innovation Solution
A nonvolatile semiconductor memory device with a control circuit that applies specific voltages to the gates of memory cells in non-selected memory strings, including a read pass voltage and a ground potential, to form a well-type potential and curb leak current, while also utilizing a back gate transistor to enhance this effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional methods (ground potential or negative potential to select transistor gate) are used to curb leak current, then leak current is reduced to some extent, but the reduction is insufficient for further increasing memory capacity and bit density
Solution Approach 1:
The patent applies different voltages to different memory cells within the same non-selected memory string based on their position. Specifically, a first voltage is applied to memory cells in a first region and a second voltage (different from the first) is applied to memory cells in a second region. This local differentiation creates more effective potential barriers at critical locations where leak current occurs, providing superior leak current curbing compared to uniform voltage application, thereby enabling further increases in memory capacity and bit density.
Solution Approach 2:
The patent changes the voltage parameter applied to memory cell gates in non-selected memory strings. Instead of using a single uniform voltage (ground or negative potential), the patent applies at least two different voltages to different regions of memory cells within the same memory string. This parameter variation optimizes the potential distribution to more effectively suppress leak current, addressing the insufficiency of conventional uniform voltage methods for achieving higher memory capacity.
2Object-affected harmful factors
If the number of memory strings connected to one bit line is decreased to curb leak current, then leak current is reduced, but memory density and capacity are limited
Solution Approach 1:
The patent implements local quality control by applying different voltages to memory cells in different regions of non-selected memory strings. This creates spatially varying potential barriers that selectively suppress leak current at critical locations without affecting the entire memory string uniformly. Consequently, more memory strings can be connected to each bit line while maintaining low leak current, thereby increasing memory density and capacity.
3Quantity of substance
If stacking-type NAND flash memory with vertical transistors is used to improve bit density, then bit density increases, but leak current from non-selected memory strings becomes a more critical problem during read operations
Solution Approach 1:
In stacking-type NAND flash memory with vertical transistors, the patent applies different voltages to memory cells at different vertical positions or regions within non-selected memory strings. This local differentiation creates optimized potential barriers that effectively suppress leak current in the three-dimensional stacked structure, enabling high bit density while controlling the enhanced leak current problem inherent in vertical transistor configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leak current during read operations, thereby improving bit density and memory capacity by forming energy barriers and well-type potentials in non-selected memory strings, allowing for more efficient data retrieval.
Implementation Method 1
apply a first voltage to a gate of at least one of the memory cells in a non-selected memory string not subject to the read operation, and apply a second voltage lower than the first voltage to a gate of another of the memory cells in the non-selected memory string not subject to the read operation
Data Source
AI summary
A nonvolatile semiconductor memory device comprises: a memory cell array having a plurality of memory strings each having a plurality of memory cells connected in series; and a control circuit configured to execute a read operation for reading data from the memory cells included in a selected memory string from among the plurality of memory strings. During the read operation, the control circuit is configured to apply a first voltage to a gate of at least one of the memory cells in a non-selected memory string not subject to the read operation, and apply a second voltage lower than the first voltage to a gate of another of the memory cells in the non-selected memory string not subject to the read operation.