NAND Flash Memory Impurity Layers for Leakage Control
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Solution Overview
Problem
High-density NAND flash memory devices face issues with leakage currents and soft programming due to the self-boosting scheme used to prevent erroneous programming, which can lead to malfunction and are exacerbated by short-channel effects and increasing integration density.
Innovation Solution
The formation of impurity layers with specific conductivity types and concentrations at the boundaries of transistors in NAND flash memory devices, including string and ground selection transistors, to inhibit leakage currents and prevent soft programming effects, such as by forming first impurity layers with opposite conductivity type impurities and second impurity layers with the same conductivity type but higher concentration at strategic boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a self-boosting scheme is used to prevent erroneous programming of non-selected memory cells, then programming accuracy is improved, but leakage current increases due to punch-through and DIBL effects
Solution Approach 1:
The patent applies different doping concentrations locally at different positions. Higher concentration impurity layers are formed at the drain region of the string selection transistor and source region of the ground selection transistor, while lower concentration impurity layers are formed at other source/drain regions. This local variation in impurity concentration creates higher electric fields specifically where needed to suppress leakage current without affecting other regions.
Solution Approach 2:
The patent changes the electrical parameters (impurity concentration) of the transistor structure to resolve the contradiction. By introducing impurity layers with specifically controlled concentrations at strategic locations, the electrical characteristics of the device are modified to suppress punch-through and DIBL effects while maintaining the self-boosting programming accuracy.
2Productivity
If integration density is increased to improve device capacity, then productivity is improved, but soft programming problems worsen due to exacerbated short-channel effects
Solution Approach 1:
The patent applies different doping concentrations locally at different positions. Higher concentration impurity layers are formed at the drain region of the string selection transistor and source region of the ground selection transistor, while lower concentration impurity layers are formed at other source/drain regions. This local variation in impurity concentration creates higher electric fields specifically where needed to suppress leakage current without affecting other regions.
Solution Approach 2:
The patent changes the electrical parameters (impurity concentration) of the transistor structure to resolve the contradiction. By introducing impurity layers with specifically controlled concentrations at strategic locations, the electrical characteristics of the device are modified to suppress punch-through and DIBL effects.
3Reliability
If 0V is applied to the gate of the ground selection transistor to interrupt current path, then erroneous programming is prevented, but channel voltage boosting causes uncontrollable channel current
Solution Approach 1:
The patent applies different doping concentrations locally at different positions. Higher concentration impurity layers are formed at the drain region of the string selection transistor and source region of the ground selection transistor, while lower concentration impurity layers are formed at other source/drain regions. This local variation in impurity concentration creates higher electric fields specifically where needed to suppress leakage current without affecting other regions.
Solution Approach 2:
The patent applies preliminary anti-action by forming high concentration impurity layers at the drain of the string selection transistor and source of the ground selection transistor before operation. These pre-formed high-field regions counteract the harmful effects of voltage boosting and current uncontrollability that would otherwise occur during the self-boosting programming operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents leakage currents and soft programming, ensuring accurate programming operations and enabling the fabrication of higher-density nonvolatile memory devices by controlling channel and source/drain regions.
Implementation Method 1
First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors.
Implementation Method 2
Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.
Implementation Method 3
A high voltage Vpgm for programming is then applied to a selected wordline so as to carry out a programming operation by means of a Fowler-Nordheim (FN) tunneling effect.
Data Source
AI summary
A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.