NAND Flash Soft-Bit Decoding with Location-Based LLR Tables
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Solution Overview
Problem
Existing memory systems face challenges in improving operation reliability and data transfer speed due to overlapping threshold distributions in NAND flash memory, which lead to reading errors and increased latency in error correction processes.
Innovation Solution
A memory system that includes a controller maintaining multiple log likelihood ratio (LLR) tables, dynamically selecting the optimal LLR table based on the physical location or usage history of the target storage region for error correction, employing soft-decision decoding to enhance error correction accuracy and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple LLR tables are maintained and dynamically selected based on physical location or usage history, then error correction accuracy and data transfer speed are improved, but device complexity and memory resource requirements increase
Solution Approach 1:
The single LLR table is segmented into multiple LLR tables, each optimized for specific physical locations or usage histories within the NAND flash memory. The controller maintains multiple LLR tables (first LLR table, second LLR table, etc.) and selects the appropriate table based on the target storage region's characteristics, thereby improving error correction accuracy without requiring complete redesign of the entire system.
Solution Approach 2:
The controller pre-maintains multiple LLR tables with different characteristics before actual error correction operations are needed. By preparing these tables in advance and organizing them according to physical locations or usage histories, the system can quickly select the most suitable LLR table when error correction is required, reducing latency and improving data transfer speed.
2Productivity
If soft-decision decoding is employed with multiple LLR tables, then error correction speed and reliability are improved, but loss of time for table selection and management increases
Solution Approach 1:
The controller pre-organizes multiple LLR tables according to specific criteria (physical locations or usage histories) before actual error correction operations. This preliminary organization allows for rapid table selection during error correction by simply matching the target storage region's characteristics with the pre-organized tables, significantly reducing the time required for table selection and management.
Solution Approach 2:
The system implements feedback mechanisms to track usage histories of different storage regions and dynamically adjust LLR table selections. By monitoring and learning from past error patterns and correction outcomes, the controller can make more accurate table selections, improving error correction speed while minimizing the time spent on table selection through intelligent decision-making.
Data Source
AI summary
A memory system includes a nonvolatile semiconductor memory, and a controller configured to maintain a plurality of log likelihood ratio (LLR) tables for correcting data read from the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on a physical location of a target unit storage region of a read operation, and carry out correcting of data read from the target unit storage region, using one of the LLR tables selected according to the determined order.