NAND Flash LLR Lookup Tables for Faster LDPC Decoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current LDPC decoding methods in NAND-based flash memories, such as the layered min-sum algorithm, suffer from performance degradation and require multiple reads to obtain high-quality log likelihood ratios (LLRs), which negatively impacts the decoding performance and increases the time consumption of the flash memory controller.
Innovation Solution
A nonvolatile memory system that includes a controller with read circuitry and look-up tables to provide improved LLRs for LDPC decoding by reading threshold voltages of target and neighboring cells, using neighboring cell contribution LLR look-up tables to enhance the reliability of bit estimations based on physical proximity and program/erase cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple reads are performed to obtain high-quality LLRs, then the reliability of bit estimations is improved, but the time consumption and performance of the flash memory controller deteriorate
Solution Approach 1:
The patent pre-calculates and stores LLR values in look-up tables during manufacturing or initialization, based on simulated or measured threshold voltage distributions. During actual decoding operations, the controller simply queries these pre-computed tables rather than performing multiple reads or complex calculations, thus obtaining high-quality LLRs without the time penalty of multiple reads.
2Device complexity
If the layered min-sum algorithm is used for decoding, then the hardware complexity is reduced, but the decoding performance deteriorates
Solution Approach 1:
The patent modifies the input parameters to the layered min-sum algorithm by providing enhanced LLR values derived from neighboring cell information and threshold voltage distributions. This parameter enhancement allows the simpler min-sum algorithm to achieve decoding performance closer to the optimal belief propagation method, without increasing hardware complexity.
3Reliability
If normalized layered min-sum algorithm is used with attenuation factor, then the decoding performance degradation is counteracted, but the device complexity increases
Solution Approach 1:
The patent extracts and pre-computes the normalization factors and attenuation parameters during initialization, storing them in look-up tables. During actual decoding, these pre-computed values are directly applied without requiring complex real-time calculations, thus improving decoding performance while minimizing the increase in operational device complexity.
Data Source
AI summary
A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of neighboring cell contribution LLR look-up tables representative of the contribution of the neighboring cells to threshold voltage distribution of the memory storage module. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.