NAND Flash Soft Decoding With Recursive LLR Interference Updates

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Solution Overview

Problem

Conventional methods for removing the effect of neighboring wordlines and bitline interference in NAND flash memory devices require large SoC area due to the need for lookup tables and are not adaptive to interference changes over the lifespan of the drive.

Innovation Solution

A method that models bitline and wordline interference using a linear model with coupling coefficients as functions of program erase cycles, read disturb, and retention time, and adapts these coefficients using a minimum mean square error estimator for on-the-fly interference removal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If lookup tables are used to remove neighboring wordline effects, then decoding accuracy is improved, but SoC area increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoidSoC area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent changes the approach from using static lookup tables to dynamically calculating interference values based on program erase cycles, read disturb, and retention time parameters. This allows the system to adapt to changing interference conditions without requiring large storage tables, thereby maintaining decoding accuracy while reducing SoC area.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the mechanical lookup table storage and retrieval system with a computational model that calculates interference values on-the-fly using mathematical relationships. This substitution eliminates the need for large hardware tables while achieving the same or better decoding accuracy through adaptive parameter-based calculations.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Object-affected harmful factors

If conventional interference removal methods are used, then neighboring wordline effects are reduced, but adaptability to interference changes over drive lifespan is lost

Engineering Contradiction:
Improveneighboring wordline interferenceVSAvoidadaptability to interference changes
Core Design Contradiction:
Object-affected harmful factorsVSAdaptability or versatility

Solution Approach 1:

The patent introduces dynamic adaptation by making the interference removal parameters (program erase cycles, read disturb, retention time) changeable over time based on actual drive usage conditions. This allows the system to continuously adapt to evolving interference patterns throughout the drive's operational lifespan, unlike static conventional methods.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements feedback mechanisms where decoding performance and interference measurements are used to adjust and refine the interference removal parameters over time. This feedback loop enables the system to learn from actual operating conditions and optimize its interference compensation strategy dynamically.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If complex decoding algorithms are used to handle interference, then decoding accuracy is improved, but computational complexity increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoidcomputational complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the interference removal process into distinct, manageable components: calculating neighboring wordline interference based on program erase cycles and retention time, calculating bitline interference based on read disturb, and combining these with the original LLR values. This segmentation simplifies the overall computational complexity while maintaining comprehensive interference compensation.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10877840B2Dynamic neighbor and bitline assisted correction for NAND flash storage
Publication Date: 2020.12.29 SK HYNIX INC
  • US10877840B2 patent drawing
  • US10877840B2 patent drawing
  • US10877840B2 patent drawing

AI summary

A storage system includes memory cells arranged in an array and a memory controller coupled to the memory cells for controlling operations of the memory cells. The memory controller is configured to perform a read operation in response to a read command from a host, perform a first soft decoding of data from the read operation using existing LLR (log likelihood ratio) values stored in the memory controller, update existing LLR values using LLR values from neighboring memory cells and existing weight coefficients that account for influence from the neighboring memory cells. The memory controller is also configured to perform a second soft decoding using the updated LLR values. If the second soft decoding is successful, the memory controller performs a recursive update of weight coefficients to reflect updated influence from neighboring memory cells and stores the updated weight coefficient in the memory controller for use in further decoding.