Multi-Chip NAND Flash LUN Assignment via Master-Slave Detection

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Solution Overview

Problem

In multi-chip NAND flash memory packages, existing technologies face challenges in allowing each memory chip to recognize its logical unit number (LUN) and the total number of chips loaded, which is essential for efficient data access and storage management.

Innovation Solution

A semiconductor integrated circuit with a multi-chip package and a controller that includes a logic control unit within each memory chip, capable of detecting potentials from wiring pads to determine the LUN and total number of chips, using pulse counts and status response commands to set the LUN and MCM information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If each memory chip is recognized by rewriting a register stored in a ROM area from the outside after package sealing, then the LUN and total chip number can be set, but the process becomes complex and time-consuming

Engineering Contradiction:
Improvechip recognition accuracyVSAvoidrecognition process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-configuring the recognition mechanism during package assembly. The master chip is designated in advance (e.g., through physical positioning or initial electrical connection), and the LUN assignment process is initiated automatically upon power-up, eliminating the need for complex external register rewriting procedures.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements self-service through automatic LUN assignment. When power is supplied, the master chip automatically detects the presence of slave chips and assigns LUNs based on detection results, without requiring external intervention or complex manual configuration procedures.

Inventive Principle:
Principle #25Self-service

2Adaptability or versatility

If external rewriting is used to set LUN and total chip number, then configuration can be done, but the operation time increases

Engineering Contradiction:
Improveconfiguration capabilityVSAvoidinitialization time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The system performs preliminary configuration setup during package assembly, with the master chip designated in advance. Upon power-up, the automatic detection and LUN assignment process begins immediately, eliminating the time-consuming external rewriting operations required by conventional methods.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The memory chips perform self-configuration automatically upon power-up. The master chip detects slave chips and assigns LUNs autonomously without requiring external rewriting operations, significantly reducing initialization time while maintaining full configuration capability.

Inventive Principle:
Principle #25Self-service

3Ease of operation

If automatic recognition is implemented, then the process is simplified, but additional control logic is required in each chip

Engineering Contradiction:
Improvechip recognition easeVSAvoidinternal circuit complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The system implements self-service through automatic LUN assignment. When power is supplied, the master chip automatically detects the presence of slave chips and assigns LUNs based on detection results, without requiring external intervention or complex manual configuration procedures.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11749355B2Semiconductor integrated circuits, multi-chip package, and operation method of semiconductor integrated circuits
Publication Date: 2023.09.05 KIOXIA CORP
  • US11749355B2 patent drawing
  • US11749355B2 patent drawing
  • US11749355B2 patent drawing

AI summary

According to a certain embodiment, the semiconductor integrated circuit includes a multi-chip package comprising a plurality of memory chips, and a controller configured to control the multi-chip package. Each of the plurality of memory chips includes a logic control unit including a logic unit circuit configured to detect a potential from a wiring pad. The logic unit circuit determines a master chip or a slave chip on the basis of the potential detected from the wiring pad, the master chip transmits a pulse count and a status response command to the slave chip, so that the slave chip sets a logical unit number of its own memory chip, and the master chip sets a total number of chips loaded on the basis of status information from the slave chip.