NAND Flash Memory LUN Coupling Control to Reduce Unnecessary Current
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Solution Overview
Problem
Existing memory devices, particularly NAND flash memories, face inefficiencies in managing electrical coupling between logical unit numbers (LUNs) during data input/output operations, leading to unnecessary current consumption and operational inefficiencies.
Innovation Solution
Implementing a control mechanism that manages the electrical coupling between LUNs using address and command signals, specifically through the use of command latch enable (CLE) and address latch enable (ALE) signals to control the active and standby states of receivers in LUNs, minimizing unnecessary current flow during write and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If electrical coupling is maintained in all LUNs during data operations, then data input/output operations can be performed without delay, but current consumption increases due to unnecessary coupling in non-selected LUNs
Solution Approach 1:
The patent applies dynamics by making the electrical coupling state changeable based on operational needs. The control circuit dynamically switches between coupled and decoupled states for different LUNs: during write operations, the selected LUN remains coupled while others are decoupled; during read operations, all LUNs are coupled to receive data simultaneously. This dynamic state management resolves the contradiction between maintaining operational readiness and reducing unnecessary current consumption.
Solution Approach 2:
The patent segments the electrical coupling control for each LUN independently through individual control circuits. Each LUN has its own control circuit that can independently manage its coupling state to the data input/output lines. This segmentation allows the system to couple only the necessary LUNs during operations rather than maintaining coupling for all LUNs, thereby reducing overall current consumption while maintaining productivity.
2Loss of time
If electrical coupling is maintained in all LUNs, then switch-over between LUNs can be performed quickly, but current consumption increases due to continuous coupling
Solution Approach 1:
The patent applies preliminary action by maintaining the selected LUN in a coupled state before the actual data operation begins. The control circuit keeps the selected LUN coupled to the data input/output lines during the entire operation cycle, ensuring that no time is lost for re-coupling during the operation. This preliminary maintenance of coupling state eliminates switch-over delays while avoiding the need to continuously couple all LUNs, thus reducing current consumption.
3Ease of operation
If all LUNs are coupled to data input/output lines, then data can be received by any LUN without delay, but unnecessary current flows through non-selected LUNs
Solution Approach 1:
The patent applies local quality by providing different coupling states to different LUNs based on their specific operational roles. The selected LUN(s) that need to perform data operations maintain electrical coupling to the data input/output lines, while non-selected LUNs are decoupled. This localized quality control ensures that data reception capability is maintained for active LUNs while eliminating unnecessary current flow through inactive LUNs.
Data Source
AI summary
A memory system includes a memory device and a memory controller. The memory device includes a memory cell array configured to store data, a data input and output interface configured to receive a command, an address, and data to be written into the memory cell array from the memory controller, and to output data read from the memory cell array to the memory controller, and a control circuit configured to control the memory cell array to perform an operation in response to receipt of a command while a first control signal is being asserted by the memory controller and receipt of an address subsequent to the command while a second control signal is being asserted by the memory controller.


