NAND Flash LUN Selection Cycle for Lower Command Overhead
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Solution Overview
Problem
Existing semiconductor systems face increased command overhead and complexity in NAND flash memory systems due to the use of separate command and address interfaces, which degrade performance and complicate internal circuits for parallel operations.
Innovation Solution
A semiconductor system with a first and second semiconductor apparatus that utilizes a LUN selection cycle, enabling selective command and address latch signals to simplify signal transmission, reducing command overhead by optimizing the sequence of signal transmission cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a separate command and address interface (SCA) method is used, then command overhead is partially reduced, but internal circuit complexity increases for parallel operations
Solution Approach 1:
The patent combines the command interface and address interface into a unified input/output bus, eliminating the need for separate command and address buses. This merging approach reduces the overall interface complexity and removes the need for complex internal circuitry required for parallel command and address operations, while still achieving efficient command execution through the unified bus structure.
Solution Approach 2:
The unified input/output bus serves multiple functions by handling both command and address signals through the same physical interface. This multi-functional approach allows the single bus to replace the traditional separate command bus and address bus, reducing interface complexity while maintaining the ability to perform parallel operations through intelligent signal multiplexing and control.
2Speed
If operating frequency is increased, then system performance improves, but command overhead increases causing performance deterioration
Solution Approach 1:
The unified input/output bus enables continuous data flow for both commands and addresses without the interruptions and overhead associated with switching between separate command and address interfaces. This continuous operation allows the system to maintain high operating frequencies by eliminating the command overhead that would otherwise occur at each interface transition, ensuring that useful actions (data transmission) continue without unnecessary delays.
3Device complexity
If a unified input and output bus is used, then interface complexity is reduced, but signal differentiation becomes more challenging
Solution Approach 1:
The system employs control signals and timing mechanisms that provide feedback to distinguish between command and address signals on the unified bus. By using enable signals, timing sequences, and state machine control, the receiver can reliably differentiate between command and address phases, ensuring accurate signal interpretation despite the unified interface structure.
Data Source
AI summary
A semiconductor system includes a first semiconductor apparatus and a second semiconductor apparatus. The first semiconductor apparatus transmits an address signal during an address cycle after transmitting a command signal during a command cycle. The first semiconductor apparatus transmits a selection signal during a logical unit number selection cycle before the command cycle. The second semiconductor apparatus performs a data input and output operation based on the selection signal, the command signal, and the address signal.