NAND Flash Storage Mapping Table Expansion Circuit
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Solution Overview
Problem
NAND flash devices face increased latency due to the limited data buffer space for storing storage mapping tables, which is exacerbated by the need for the host to acquire and convert the table format for logical-to-physical address conversion, leading to inefficiencies in data access.
Innovation Solution
An apparatus and method utilizing a DMA controller and expanding circuit to generate a storage mapping table by reading and expanding physical addresses, allowing the controller to transmit an expanded address format to the host without storing the original address in the flash memory unit, thereby reducing latency and buffer space requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the NAND flash device stores only a portion of the storage mapping table in the data buffer for fast look-up, then the buffer space requirement is reduced, but the latency for obtaining data increases when the logical address cannot hit the partial storage mapping table
Solution Approach 1:
The expanding circuit performs preliminary expansion of physical addresses to the specification format and stores them in the data buffer in advance. This preliminary action ensures that when the host requests storage mapping table data, the expanded format data is already available in the buffer, eliminating the need for real-time conversion and reducing latency while maintaining compact storage.
2Ease of operation
If the host acquires the storage mapping table from the NAND flash device and performs logical-to-physical address conversion, then the host can access data using physical addresses, but the time required for generation and conversion of the storage mapping table increases
Solution Approach 1:
The expanding circuit acts as an intermediary component between the storage mapping table data and the host. It automatically performs the format expansion from the native compact format to the specification format required by the host, enabling the host to access data using physical addresses in the expected format without manually performing conversion operations, thus reducing generation time while maintaining ease of operation.
3Quantity of substance
If the NAND flash device uses native format for storing physical addresses, then the storage efficiency is improved, but the compatibility with the flash memory specification decreases requiring format conversion
Solution Approach 1:
The expanding circuit introduces a new dimension of data representation by transforming the compact native format physical addresses into the expanded specification format. This dimensional transformation adds the necessary address bits and formatting structure required by the flash memory specification, enabling compatibility with standard hosts while preserving the storage efficiency of the native format in the buffer.
Data Source
AI summary
The invention introduces an apparatus for generating a storage mapping table at least including a direct memory access controller for reading first physical location (PL) address corresponding to a logical location of the storage mapping table; an expanding circuit for obtaining the first PL address and expanding the first PL address into second PL address by appending data bits that originally provide different information from a physical address of the flash memory unit to the first PL address; and a controller for transmitting the second PL address without transmitting the first PL address stored in the flash memory unit to a host.