NAND Flash Memory Block Programming and Read Count Management

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Solution Overview

Problem

Increasing the size of blocks of memory cells in NAND flash memory leads to latency issues due to housekeeping tasks, limiting the physical size of blocks to meet customer and industry standards, and programming of memory cells from one end to the other can result in unacceptable program disturb in lower data states.

Innovation Solution

Implementing a method to program memory cells in a block from a different end than usual, using GIDL to seed unselected channel regions and reducing the precharge voltage level to mitigate Vpass disturb, and maintaining separate read counts for each portion of a block to prevent premature read count leveling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the size of blocks of memory cells is increased, then memory density is improved, but latency issues arise due to housekeeping tasks

Engineering Contradiction:

Improvememory densityVSAvoidlatency

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The block of memory cells is divided into multiple portions, each with separate read count registers. This segmentation allows independent management of read counts for different portions, enabling parallel housekeeping operations and reducing overall latency while maintaining high memory density.

Inventive Principle:

Principle #1Segmentation

2Reliability

If memory cells are programmed from one end to the other, then programming completeness is achieved, but program disturb in lower data states becomes unacceptable

Engineering Contradiction:

Improveprogramming completenessVSAvoidprogram disturb

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies GIDL to seed unselected channel regions, effectively inverting the traditional approach by pre-charging unselected regions before programming. This inversion mitigates program disturb in lower data states while ensuring complete programming of all memory cells in the block.

Inventive Principle:

Principle #13The other way round (Inversion)

3Object-affected harmful factors

If precharge voltage level is reduced to mitigate Vpass disturb, then program disturb is minimized, but programming efficiency may be affected

Engineering Contradiction:

ImproveVpass disturbVSAvoidprogramming efficiency

Core Design Contradiction:

Object-affected harmful factorsVSProductivity

Solution Approach 1:

The patent optimizes the precharge voltage level parameter to balance between mitigating Vpass disturb and maintaining programming efficiency. By carefully selecting the precharge voltage level, the system achieves reduced program disturb while preserving acceptable programming speeds.

Inventive Principle:

Principle #35Parameter changes

4Measurement precision

If separate read counts are maintained for each portion of a block, then read count leveling accuracy is improved, but device complexity increases

Engineering Contradiction:

Improveread count leveling accuracyVSAvoidregister management complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements separate read count registers for different portions of the memory block, segmenting the read count management system. This segmentation improves read count leveling accuracy by tracking reads per portion independently, while the modular structure keeps complexity manageable through systematic organization.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces latency issues by optimizing programming operations and minimizing program disturb, while also ensuring accurate read count leveling by accounting for separate read operations in different portions of the memory block.

Implementation Method 1

using GIDL to seed unselected channel regions and reducing the precharge voltage level to mitigate Vpass disturb

Methodology Applied

Scientific EffectGIDL (Gate-Induced Drain Leakage):

Data Source

PatentUS11328782B2Memory architecture for access of multiple portions of a block of memory cells

Publication Date: 2022.05.10 MICRON TECHNOLOGY INC

AI summary

Memory might have a controller configured to program a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and program the second portion of memory cells in an order from the particular end to the different end. Memory might further have a controller configured to increment first and second read counts in response to performing a read operation on a memory cell of a block of memory cells, reset the first read count in response to performing an erase operation on a first portion of the block of memory cells, and reset the second read count in response to performing an erase operation on the second portion of the block of memory cells.