NAND Flash Memory Cell Array Segmentation for Self-Boosting
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Solution Overview
Problem
The challenge is to increase the storage capacity of flash memory devices while maintaining control over the interval and width of threshold voltage distributions as the number of data bits increases, and to address the issue of inadequate self-boosting in NAND flash memory devices when augmenting the number of word lines.
Innovation Solution
The solution involves configuring a non-volatile memory device with a memory cell array that includes a combination of single level cells (SLCs) and multi-level cells (MLCs) across multiple word lines, where SLCs are used adjacent to select lines and MLCs are used between them to store varying bits of information, effectively increasing the number of word lines and storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of data bits stored in each memory cell is increased to augment storage capacity, then the storage capacity increases, but the interval between threshold voltages and width of threshold voltage distributions becomes narrower and harder to control
Solution Approach 1:
The memory cell array is divided into multiple blocks, where some blocks use SLC configuration (storing 1 bit per cell) and others use MLC configuration (storing 2 or more bits per cell). This segmentation allows the system to achieve high overall storage capacity while maintaining precise threshold voltage control in the SLC blocks, thereby resolving the contradiction between storage capacity and threshold voltage distribution control.
2Quantity of substance
If the number of word lines is augmented to increase storage capacity, then the storage capacity increases, but self-boosting becomes inadequate in NAND flash memory devices
Solution Approach 1:
The memory cell array is divided into multiple blocks with different configurations. By including blocks with fewer word lines (SLC blocks) alongside blocks with more word lines (MLC blocks), the system achieves high overall storage capacity while the SLC blocks provide adequate self-boosting performance, thereby resolving the contradiction between storage capacity and self-boosting reliability.
Solution Approach 2:
Different blocks of the memory cell array are assigned different local qualities: some blocks use SLC configuration with 1 bit per cell providing strong self-boosting, while others use MLC configuration with 2 or more bits per cell providing high storage capacity. This local differentiation allows the overall system to achieve both high storage capacity and adequate self-boosting performance.
Data Source
AI summary
A non-volatile memory device increases a number of word lines and a storage capacity using a multi level cell. The non-volatile memory device addresses a problem of self-boosting not being adequately generated due to the increased number of word lines. The non-volatile memory device includes a memory cell array configured to have first memory cells for storing first bit information coupled to third word lines except a first word line adjacent to a drain select line and a second word line adjacent to a source select line, and second memory cells coupled to the first word line and the second word line. The second memory cells store second bit information that is smaller than the first bit information.