NAND Flash Memory Cell Group Segmentation for Erase Control
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Solution Overview
Problem
The challenge in NAND flash memory devices is to achieve high integration while limiting the number of memory cells erased during an erase operation, as reducing the size of select transistors is difficult, leading to increased chip size and potential operation errors due to hot-carrier injection.
Innovation Solution
The solution involves dividing memory cells into groups and using dummy elements at group boundaries to apply erase voltages selectively, allowing for independent erase operations of each group, thereby controlling the number of cells erased and reducing operation errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells per block is increased to achieve high integration, then integration density is improved, but the number of memory cells erased during erase operation increases, leading to more operation errors due to hot-carrier injection
Solution Approach 1:
The memory cell string is divided into multiple groups (first memory cell group and second memory cell group) with dummy elements inserted between them. During erase operations, only the selected group is erased while the other group remains intact, thereby limiting the number of cells subject to hot-carrier injection and reducing operation errors while maintaining high integration density.
Solution Approach 2:
Dummy elements are inserted as intermediary components between the first and second memory cell groups. These dummy elements act as buffers that absorb hot-carrier effects during erase operations, protecting the non-selected memory cell group from damage and reducing operation errors.
2Quantity of substance
If select transistor size is reduced to increase integration density, then integration density is improved, but manufacturing precision and reliability deteriorate
Solution Approach 1:
The memory block is segmented into multiple independently erasable groups, allowing the use of larger, more reliably manufactured select transistors while maintaining high overall integration density through the grouped structure.
3Quantity of substance
If select transistor size is reduced to increase integration density, then integration density is improved, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The memory block is divided into multiple independently erasable groups, allowing selective erase operations on specific groups rather than the entire block. This segmentation enables more efficient erase control and reduces the complexity of managing large numbers of cells.
Solution Approach 2:
Instead of erasing the entire memory block, only the selected memory cell group is erased while other groups remain intact. This partial action approach simplifies the erase control mechanism by limiting the scope of operation to only the necessary cells.
Data Source
AI summary
A method of operating a semiconductor memory device includes a memory array having memory cell strings including a first and a second memory cell groups having memory cells, a first and a second dummy elements, a drain select transistor and a source select transistor, wherein the first memory cell group and the second memory cell group are arranged between the drain select transistor and the source select transistor; connecting electrically the first memory cell group to the second memory cell group during a program operation or a read operation of the first memory cell group or the second memory cell group; and performing separately an erase operation of the first memory cell group and an erase operation of the second memory cell group, selecting simultaneously one of the first dummy element and the second dummy element during the erase operation of the selected memory cell group.