NAND Flash Memory Cell Group Voltage Control for Erase Verification
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Solution Overview
Problem
The miniaturization of NAND flash memory cells leads to reduced cell current, making it difficult to charge bit lines within a predetermined time during erase verification operations, and results in reduced low-voltage margins, causing erase failures and uneven write characteristics across memory strings.
Innovation Solution
A non-volatile semiconductor storage device with a memory cell array divided into multiple groups, where different control voltages are applied to word lines during erase verification, allowing the same voltage to be applied to memory cells within the same group, and a controller adjusts the number of memory cell groups based on access counts to optimize erase verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are miniaturized to increase memory capacity, then memory capacity is improved, but cell current is reduced making it difficult to charge bit lines within predetermined time
Solution Approach 1:
The memory cell array is divided into multiple banks, and within each bank, memory cells are organized into multiple groups (first group and second group). This segmentation allows independent voltage control of different groups, enabling optimized erase verification operations where one group can be verified while another undergoes erase, thereby improving overall charge speed and memory capacity utilization.
Solution Approach 2:
Before performing erase verification on a first group of memory cells, a read operation is preliminarily performed on a second group of memory cells. This preliminary action allows the system to prepare and switch voltage levels efficiently, ensuring that when erase verification is needed, the appropriate voltage conditions are already in place, thus maintaining fast charge speeds even as memory capacity increases.
2Quantity of substance
If memory cells are miniaturized, then memory capacity is improved, but low-voltage margin is reduced causing erase failures
Solution Approach 1:
Different voltage levels are applied to different groups of memory cells based on their specific operational state. The first group receives a first voltage level during erase verification while the second group receives a second voltage level. This local differentiation ensures that each group operates within its optimal voltage margin, preventing erase failures even as individual cell dimensions are reduced to increase overall capacity.
Solution Approach 2:
The system dynamically changes voltage parameters (first voltage level and second voltage level) applied to different memory cell groups during erase verification operations. By adjusting these voltage parameters based on the operational phase and group state, the system maintains adequate voltage margins for miniaturized cells, ensuring reliable erase verification while accommodating reduced cell size for higher capacity.
3Quantity of substance
If memory cells are miniaturized, then memory capacity is improved, but write characteristics become uneven across memory strings
Solution Approach 1:
Memory cells are segmented into multiple groups within each bank, allowing independent voltage control. This segmentation enables the system to apply tailored voltage conditions to different groups during write and verify operations, compensating for variations in write characteristics that arise from miniaturization and ensuring uniform performance across all memory strings regardless of position.
Solution Approach 2:
Different voltage levels are applied to different groups of memory cells based on their specific operational requirements and physical characteristics. This local quality approach ensures that memory cells at different positions within the array receive appropriate voltage conditions, maintaining uniform write characteristics across the entire memory array even as individual cells are miniaturized to increase capacity.
Data Source
AI summary
A non-volatile semiconductor storage device includes: a memory cell array including memory strings, each of the memory strings having: a first end; a second end; and a plurality of memory cells connected in series between the first end and the second end, the memory cells being categorized into memory cell groups; a first end that is one end of the memory string; and a second end that is the other end of the memory string; first selection transistors connected to the respective first ends of the memory strings; a plurality of second selection transistors connected to the respective second ends of the memory strings; bit lines connected to the respective second selection transistors; word lines connected to the memory cells; and a control circuit configured to apply different control voltages to the respective word lines.