NAND Flash Memory Controller Read Voltage Adjustment
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Solution Overview
Problem
MLC NAND flash memory devices face read errors due to insufficient read margin and broadening threshold voltage state distribution, which complicates operations and reduces reliability, especially as they age.
Innovation Solution
A non-volatile memory device with a memory controller that includes a bit counter to count binary digits of page data read by test voltages, a register to store count values, and a read voltage adjuster to determine an optimal read voltage by calculating delta values and selecting a voltage range with a minimum number of memory cells, thereby minimizing read errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read voltage adjustment operations are separately performed to reduce read errors, then reliability is improved, but operation speed deteriorates
Solution Approach 1:
The patent combines the read voltage adjustment operation with the normal read operation by integrating the bit counting function into the existing read path. The memory controller counts bits during the regular read operation and uses this information to adjust read voltages, eliminating the need for separate adjustment operations and thereby maintaining high operation speed while improving reliability.
Solution Approach 2:
The memory controller performs self-adjustment of read voltages by autonomously counting bits from readout page data and determining optimal voltages without requiring external intervention or separate calibration procedures. This self-service mechanism enables continuous optimization of read reliability while maintaining operational efficiency.
2Reliability
If multiple test read voltages are applied to determine optimal read voltage, then read error reduction is improved, but processing time increases
Solution Approach 1:
The patent applies multiple test read voltages in advance during manufacturing or initial operation to establish a voltage lookup table that maps bit count patterns to optimal read voltages. This preliminary action enables the memory controller to quickly determine the appropriate read voltage during normal operation without performing multiple test reads each time, thereby reducing processing time while maintaining high reliability.
Solution Approach 2:
The patent creates a voltage lookup table that stores the relationship between bit count patterns and optimal read voltages based on preliminary testing. During normal operation, the controller copies this pre-established mapping information to quickly determine read voltages without repeating the full testing process, thus minimizing processing time while ensuring accurate voltage selection for error reduction.
3Duration of action of stationary object
If threshold voltage state distribution broadens with passage of time, then memory device aging is accelerated, but read margin is reduced
Solution Approach 1:
The patent implements dynamic read voltage adjustment that adapts to the broadening threshold voltage distribution over time. The memory controller continuously monitors bit count patterns from readout data and adjusts read voltages accordingly, allowing the system to maintain adequate read margins even as the memory device ages and threshold voltage distributions broaden.
Solution Approach 2:
The patent employs feedback mechanisms where the memory controller counts bits from readout page data and uses this information to determine and adjust optimal read voltages. This closed-loop feedback system continuously compensates for threshold voltage drift and distribution broadening that occur with aging, thereby maintaining read reliability throughout the memory device's operational lifetime.
Data Source
AI summary
A non-volatile memory device according to example embodiments includes at least one NAND flash memory and a memory controller configured to control the NAND flash memory. The memory controller comprises a bit counter configured to count a number of first binary digit of each of first to N-th readout page data, the first to N-th readout page data being respectively read by first to N-th test read voltages, a register configured to store first to N-th count values with respect to the first to N-th readout page data output from the bit counter, and a read voltage adjuster configured to compare the first to N-th count values to determine a read voltage, where N is an integer greater than 1.