NAND Flash Memory Controller Read Voltage Correction

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Solution Overview

Problem

Current memory systems face challenges in efficiently managing read voltage corrections across multiple cell units in NAND flash memory, leading to increased error bits and memory capacity requirements, particularly due to the need for frequent patrol processing to determine correction amounts for each cell unit.

Innovation Solution

The memory system employs a read voltage correction circuit and DRAM interface to calculate and update correction amounts for read voltages, using representative correction amounts for patrol processing and conversion information to apply these corrections across cell units, reducing the need for individual storage and frequent patrol processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If individual correction amounts are determined for each cell unit through frequent patrol processing, then read accuracy is improved, but memory capacity requirements and processing time increase

Engineering Contradiction:
Improveread accuracyVSAvoidpatrol processing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The memory system divides cell units into multiple groups and determines correction amounts for representative cell units of each group rather than every cell unit. This segmentation approach maintains read accuracy for all cell units while significantly reducing the frequency and time of patrol processing operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system copies the correction amount from a representative cell unit to other cell units within the same group. By determining the correction amount for one representative cell unit and applying it to multiple cell units, the system reduces the number of patrol processing operations needed while maintaining read accuracy across all cell units.

Inventive Principle:
Principle #26Copying

2Measurement precision

If individual correction amounts are stored for each cell unit, then read voltage accuracy is improved, but memory capacity requirements increase

Engineering Contradiction:
Improveread voltage accuracyVSAvoidmemory capacity
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The system segments cell units into groups and stores correction amounts only for representative cell units of each group. This reduces the quantity of correction amount data that must be stored in the memory system while maintaining read voltage accuracy for all cell units through the use of conversion information.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The representative correction amount stored for each group serves multiple cell units within that group. This multi-functional approach allows a single stored correction amount to be applied universally across multiple cell units, reducing overall memory capacity requirements while maintaining accuracy.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Quantity of substance

If conversion information is used to apply correction amounts across cell units, then the need for individual storage is reduced, but processing complexity increases

Engineering Contradiction:
Improvestorage requirementsVSAvoidprocessing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The system changes parameters by storing conversion information that enables transformation of the representative correction amount into applicable correction values for other cell units. This parameter change approach reduces storage requirements while managing processing complexity through standardized conversion operations.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11424002B2Memory system that includes a NAND flash memory and a memory controller
Publication Date: 2022.08.23 KIOXIA CORP
  • US11424002B2 patent drawing
  • US11424002B2 patent drawing
  • US11424002B2 patent drawing

AI summary

According to one embodiment, a memory system includes a nonvolatile memory including a plurality of cell units, each of the plurality of cell units including a plurality of memory cells, and a memory controller. The memory controller is configured to: read first data from a first cell unit, using a first correction amount of a read voltage; identify an address of an error bit in the first data; update the first correction amount to a second correction amount, based on the first data and the address of the error bit of the first data; and read second data from a second cell unit different from the first cell unit, using a third correction amount based on the second correction amount.