NAND Flash Memory Page Configuration with Dynamic ECC Allocation
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Solution Overview
Problem
Current NAND flash memory devices face inefficiencies due to the lack of a standardized ECC algorithm implementation, leading to either unnecessary waste of chip space by including maximum ECC bytes or insufficient ECC bytes for certain algorithms, which can prevent the use of desired error correction methods.
Innovation Solution
A NAND flash memory page configuration that includes an additional cells array, which can be dynamically designated for either additional ECC bytes or redundancy cells, allowing for flexible allocation based on the specific ECC algorithm requirements, using a multiplexer to control the designation of these cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory areas for storing the maximum number of ECC bytes per page are included, then stronger ECC algorithms can be supported, but chip size is wasted for applications requiring fewer ECC bytes
Solution Approach 1:
The patent implements a dynamic memory configuration where the spare area can be reconfigured between different ECC byte allocations. A multiplexer dynamically routes memory cells between the main array and spare array, allowing the system to adapt the ECC capacity based on the specific algorithm requirements at runtime, thus avoiding fixed over-provisioning
Solution Approach 2:
The patent changes the parameter of ECC byte allocation from a fixed value to a variable that can be adjusted based on the ECC algorithm being used. By modifying the configuration parameters through multiplexer control, the system can optimize the balance between reliability and chip space utilization for different applications
2Loss of substance
If memory areas for storing fewer ECC bytes per page are included, then chip size is optimized, but stronger ECC algorithms cannot be implemented
Solution Approach 1:
The patent creates a universal memory configuration that can support multiple ECC algorithms with different byte requirements. The spare area serves multiple functions by being reconfigurable between different ECC capacities, allowing the same chip to universally support both lightweight and heavy-duty ECC algorithms based on application needs
Solution Approach 2:
The system dynamically adjusts the ECC capacity by reconfiguring the multiplexer connections, enabling the memory device to adapt its reliability characteristics to match the specific algorithm requirements, thus optimizing chip space while maintaining the capability to implement stronger ECC when needed
3Device complexity
If fixed memory configuration is used, then device complexity is reduced, but adaptability to different ECC algorithms is limited
Solution Approach 1:
The patent introduces dynamic reconfigurability through a multiplexer that can switch between different memory mappings. This adds controlled complexity only where needed - the multiplexer and control logic are minimal additions that enable significant adaptability to different ECC algorithms without overwhelming the system
Solution Approach 2:
The system uses parameter changes in the form of configuration bits or control signals that modify the multiplexer routing. This allows the memory device to adapt to different ECC algorithms by changing operational parameters rather than requiring fundamentally different hardware configurations, balancing simplicity and versatility
Data Source
AI summary
A method, apparatus and system providing a memory device having an array of cells which may be selectively designated for either error correction code use or redundancy cell use.