NAND Flash Memory Parallel Block Access
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Solution Overview
Problem
Conventional NAND flash memories face challenges in improving random access performance while maintaining the benefits of increased storage capacity and readout speed, particularly due to the limitations of the ABL sense scheme and lack of parallel operation for random page addresses.
Innovation Solution
The design incorporates a NAND flash memory architecture with separate bit lines and sense amplifiers for each block, allowing for independent control of even and odd-numbered columns, enabling parallel read/write operations across multiple blocks within the same memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the page length is increased to improve readout speed per unit using the ABL scheme, then the storage capacity in one page is increased, but the random access performance deteriorates
Solution Approach 1:
The memory cell array is divided into multiple blocks (first block, second block, etc.), each capable of independent read/write operations. This segmentation allows the system to handle random page addresses by selecting specific blocks, thereby improving random access performance while maintaining the benefits of increased page length through the ABL scheme in each block.
Solution Approach 2:
The patent introduces a block dimension to the traditional page-length optimization approach. Instead of only increasing page length within a single block, the system now operates across multiple blocks simultaneously, adding a spatial dimension (block selection) to the access hierarchy that enables efficient random access while preserving sequential read performance.
2Speed
If separate bit lines and sense amplifiers are provided for each block to enable parallel operations, then random access performance is improved, but the device complexity increases
Solution Approach 1:
The bit lines and sense amplifiers are segmented by block, with each block having its own dedicated resources. This segmentation enables independent parallel operations on different blocks, improving random access performance. The complexity is managed by organizing these resources in a systematic, modular fashion that allows efficient control and routing.
Data Source
AI summary
A NAND flash memory having a memory cell array formed of a plurality of blocks including memory cell transistors arranged in a matrix form. The NAND flash memory has a first bit line; a first sense amplifier connected to the first bit line, the first sense amplifier sensing or controlling a potential on the first bit line; a second bit line; and a second sense amplifier connected to the second bit line to sense or control a potential on the second bit line. The NAND flash memory has a first drain side selection gate line; a second drain side selection gate line; a third drain side selection gate line; a fourth drain side selection gate line; a first source side selection gate line; and a second source side selection gate line. The NAND flash memory has a first block; a second block; and a decoder which turns on one of the first and third drain side selection MOS transistors and turns off the other, and which turns on one of the third and fourth drain side selection MOS transistors and turns off the other.