NAND Flash Memory Recovery from Asynchronous Power Loss

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Solution Overview

Problem

Asynchronous power loss (APL) during programming in NAND flash memory devices can lead to data corruption and errors, as incomplete programming of pages results in fake empty or fake programmed pages, causing inefficiencies and potential data loss.

Innovation Solution

A method is implemented where the controller determines the number of zeros in a physical page to decide whether to write dummy data, using this count to differentiate between genuine and fake programmed pages, thereby avoiding double-writing of dummy data and minimizing errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the controller writes dummy data to all physical pages after asynchronous power loss, then data integrity is improved, but storage efficiency deteriorates due to unnecessary writes to genuine empty pages

Engineering Contradiction:
Improvedata integrityVSAvoidstorage efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The controller performs preliminary classification of physical pages into genuine empty pages and fake programmed pages before writing dummy data. By counting zero bits and comparing against thresholds, the controller identifies which pages actually need dummy data writes, preventing unnecessary writes to genuine empty pages while ensuring fake programmed pages are properly corrected.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses the existing data pattern (zero bit count) in the physical pages to automatically determine which pages require dummy data writes. The controller leverages the natural state of the pages after power loss to make intelligent decisions, eliminating the need for complex external verification processes.

Inventive Principle:
Principle #25Self-service

2Measurement precision

If the controller reads and analyzes every physical page to determine its status, then accuracy in identifying fake programmed pages is improved, but processing time increases

Engineering Contradiction:
Improveidentification accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The controller changes the measurement parameter from full page content analysis to zero bit count analysis. By counting only the number of zero bits in each physical page and comparing against predefined thresholds, the system achieves sufficient identification accuracy with significantly reduced processing requirements compared to reading and analyzing every byte of every page.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

Instead of performing complete page reads and analyses, the controller performs a partial action by counting only zero bits. This partial measurement provides enough information to distinguish between genuine empty pages and fake programmed pages, achieving acceptable accuracy with less processing time and resource consumption.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11670342B2Recovery of memory from asynchronous power loss
Publication Date: 2023.06.06 MICRON TECHNOLOGY INC
  • US11670342B2 patent drawing
  • US11670342B2 patent drawing
  • US11670342B2 patent drawing

AI summary

Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of ones stored in the first physical page.