Rearranging Data Mapping in NAND Flash Memory Refresh
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Solution Overview
Problem
Memory systems, such as NAND flash memory, face read disturbance effects due to repeated read operations, leading to data integrity issues and frequent refresh operations, especially when data is repeatedly copied to the same physical address, which can shorten the lifespan of physical blocks.
Innovation Solution
A method and system for rearranging data in memory systems by determining failed logical pages based on error bits and executing refresh operations with a rearranged mapping order, offsetting physical page addresses to distribute data across different physical blocks, thereby reducing read disturbance and extending the lifespan of physical blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is repeatedly copied to the same physical address during refresh operations, then data integrity is maintained, but read disturbance effects increase and physical block lifespan is reduced
Solution Approach 1:
The patent implements dynamic mapping order adjustment where the mapping between logical pages and physical pages is changed based on refresh operation counts. The memory controller selects between initial mapping order and rearranged mapping order dynamically, preventing repeated reads on the same physical address while maintaining data integrity through periodic refresh operations.
Solution Approach 2:
The patent changes the mapping order parameter during refresh operations. By offsetting physical page addresses in the rearranged mapping order, the system alters how logical pages map to physical pages, thereby distributing read operations across different physical blocks and reducing read disturbance effects on any single block.
2Reliability
If refresh operations are executed frequently to prevent data corruption, then data integrity is improved, but memory performance deteriorates
Solution Approach 1:
The system dynamically adjusts refresh operation frequency and mapping order based on monitored error bits and refresh counts. By adapting the refresh strategy to actual memory conditions, the system maintains data integrity while avoiding excessive refresh operations that would degrade performance.
Solution Approach 2:
The memory controller monitors error bits in physical pages and uses this feedback to determine when to perform refresh operations and whether to switch between initial and rearranged mapping orders. This feedback mechanism ensures refresh operations are performed only when necessary, balancing data integrity with memory performance.
3Device complexity
If a fixed mapping order is used from logical pages to physical pages, then mapping simplicity is maintained, but read disturbance effects accumulate on the same physical blocks
Solution Approach 1:
The patent implements dynamic mapping order selection where the system switches between initial mapping order and rearranged mapping order based on refresh operation counts and error conditions. This dynamic approach prevents read disturbance accumulation while maintaining manageable complexity through systematic mapping strategies.
Solution Approach 2:
The patent segments the mapping strategy into two distinct modes: initial mapping order for normal operations and rearranged mapping order for refresh operations. This segmentation allows the system to maintain simplicity during normal operation while applying complexity only when needed to mitigate read disturbance effects.
Data Source
AI summary
Methods, systems and apparatus including computer-readable mediums for rearranging data for refresh operations in memory systems such as NAND flash memory devices are provided. In one aspect, a method includes: determining that a particular logical page in a logical block fails based on error bits in a particular physical page that is in a first physical block mapped with the logical block and corresponds to the particular logical page, logical pages in the logical block being mapped to physical pages in the first physical block with an initial mapping order, and executing a refresh operation on the first physical block with a rearranged mapping order for the logical block, the rearranged mapping order being different from the initial mapping order. For the refresh operation, the logical pages in the logical block are mapped to physical pages in a second physical block with the rearranged mapping order.