NAND Flash Memory Block Segmentation for Cell Current
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Solution Overview
Problem
NAND flash memory devices face issues with reduced cell current due to increased channel resistors, leading to pass disturb and program disturb, especially as cell sizes shrink, and fail to efficiently manage bias application during operations.
Innovation Solution
Divide one memory block into two sub memory blocks, each with its own select transistors and shared common source line, reducing the number of channel resistors and optimizing bias application to selected and non-selected word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If one memory block is divided into two sub memory blocks with separate select transistors, then cell current is increased by reducing channel resistors, but device complexity increases due to additional select transistor structures
Solution Approach 1:
The memory block is divided into two sub memory blocks, each with its own select transistors. This segmentation reduces the number of channel resistors in each sub-block, thereby increasing cell current and improving read performance while managing the complexity through structured organization
2Reliability
If bias is applied to all word lines during program operation, then program disturb is reduced, but power consumption increases and pass disturb occurs in non-selected strings
Solution Approach 1:
By dividing the memory block into two sub blocks with separate select transistors, the patent enables selective bias application to only the active sub-block during program operations. This reduces power consumption by avoiding bias application to non-selected word lines while maintaining program reliability through proper biasing of the active sub-block
3Quantity of substance
If the number of memory cells in a string is increased to improve density, then storage capacity increases, but channel resistor increases and cell current reduces
Solution Approach 1:
The patent segments the memory block into two sub blocks, effectively halving the number of cells in each string while maintaining the same total storage capacity. This segmentation reduces the channel resistor in each sub-block, thereby increasing cell current and improving read performance without sacrificing storage capacity
Data Source
AI summary
A non-volatile memory device may include a plurality of memory blocks including memory cells connected in series to bit lines, respectively. Each of the plurality of memory blocks may include a first sub memory block having a first group of memory cells, which are respectively connected in series between first select transistors connected to the bit lines, respectively, and second select transistors connected to a common source line, and a second sub memory block having a second group of memory cells, which are respectively connected in series between third select transistors connected to the bit lines, respectively, and fourth select transistors connected to the common source line.