NAND Flash Memory System Parallel Die Control
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Solution Overview
Problem
Solid-state drives (SSDs) using NAND flash memory face significant read latency issues due to die collisions, where a read request is delayed when a die is performing a write operation, leading to increased response times and reduced performance.
Innovation Solution
The implementation of a memory system that manages multiple NAND flash memory dies in parallel, using a RAID configuration to distribute data portions and parities across different dies, allowing read operations to proceed without waiting for write operations to complete by restoring data from other dies, thus reducing read latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple NAND flash memory dies are operated in parallel to improve productivity, then the output per unit time increases, but die collision occurs causing read latency to increase significantly
Solution Approach 1:
The storage system is segmented into multiple independent NAND flash memory dies, each capable of parallel operation. Data is divided into multiple portions and distributed across different dies, allowing simultaneous read and write operations on different segments without interference, thus maintaining high productivity while avoiding die collision latency.
Solution Approach 2:
A controller acts as an intermediary between the host and multiple NAND flash memory dies. It manages data distribution, monitors die operation states, and coordinates read/write requests across different dies. When die collision is detected, the controller restores data from parity information or alternative paths, preventing read latency while maintaining parallel productivity.
2Device complexity
If data is stored in a single die to simplify the system, then device complexity is reduced, but read latency increases when die collision occurs
Solution Approach 1:
Instead of storing all data in a single die, the system segments data into multiple portions and distributes them across multiple dies. This segmentation enables parallel access and avoids the read latency problem caused by die collision, while the complexity is managed through systematic data distribution protocols.
Solution Approach 2:
The system changes the storage parameter from single-die concentration to multi-die distribution. By altering how data is organized and located across the storage medium, the system achieves both reduced read latency through parallel access and manageable complexity through standardized distribution mechanisms.
3Loss of time
If RAID configuration with parity distribution is implemented to reduce read latency, then tolerance to die collision improves, but device complexity increases
Solution Approach 1:
The controller serves as an intermediary that manages the RAID configuration complexity. It handles parity calculation, data distribution, and recovery operations automatically, shielding the user from the complexity while enabling read latency reduction through intelligent data placement and recovery mechanisms across multiple dies.
Solution Approach 2:
The system creates parity copies of data and distributes them across multiple dies. These redundant copies enable rapid data restoration when die collision occurs, reducing read latency. The copying mechanism is managed systematically through the controller, which handles the complexity of maintaining consistency across multiple copies without burdening the user.
Data Source
AI summary
A memory system includes a nonvolatile memory having memory dies controlled in parallel and each including a plurality of physical blocks, and a controller. The controller manages a plurality of logical areas for storing data portions received from the host and parities calculated from the data portions, the logical areas including first and second logical areas for storing first and second parity groups, respectively. Each first parity group includes k data portions received from the host and m parities calculated therefrom. Each second parity group includes k′ data portions received from the host and m′ parities calculated therefrom. Also, the controller maps each logical area to storage locations in the non-volatile memory dies such that the data portions and the parities of any one parity group are each stored in a different physical block in a set of physical blocks selected from different non-volatile memory dies.