NAND Flash Memory Temperature Error Management

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

NAND flash memory devices experience increased bit error rates and reliability issues due to temperature variations between the time of data writing and reading, leading to unnecessary memory cell retirement and data refresh, which can reduce drive performance and capacity.

Innovation Solution

Incorporating a write temperature indicator appended to stored data and using a controller to determine the numerical temperature difference between write and read temperatures, allowing for targeted error management operations such as memory cell retirement and data refresh, thereby reducing the occurrence of undesirable outcomes like increased write amplification and drive size reduction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If temperature-related error management is implemented without write temperature indicators, then error detection capability is improved, but false positives increase leading to unnecessary memory cell retirement

Engineering Contradiction:
Improveerror detection capabilityVSAvoidfalse positive errors
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The patent applies preliminary action by storing the write temperature indicator at the time of programming data to the memory cell. This pre-recorded temperature information is then used during read operations to compare with the current read temperature, enabling the system to distinguish between temperature-induced errors and actual memory defects. This preliminary recording of temperature conditions prevents false positive errors during error management operations.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If memory cells are retired based on error rates without temperature consideration, then data integrity is improved, but drive capacity is reduced

Engineering Contradiction:
Improvedata integrityVSAvoiddrive capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies parameter changes by introducing temperature as an additional parameter in the error management decision process. Instead of relying solely on error rates, the system now considers both the error rate and the temperature difference between write and read operations. This multi-parameter approach allows the system to maintain data integrity while avoiding unnecessary retirement of memory cells that exhibit errors only under temperature variations, thereby preserving drive capacity.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If data refresh operations are performed frequently to maintain reliability, then data retention is improved, but write amplification increases

Engineering Contradiction:
Improvedata retentionVSAvoidwrite amplification
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies feedback by using the temperature difference information to dynamically adjust the error management strategy. When the temperature difference between write and read operations is small, the system can be more conservative with refresh operations. When the temperature difference is large, the system can perform refresh operations more aggressively or adjust read reference voltages. This feedback-based approach ensures data retention while minimizing unnecessary write amplification from excessive refresh operations.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10579468B2Temperature related error management
Publication Date: 2020.03.03 MICRON TECHNOLOGY INC
  • US10579468B2 patent drawing
  • US10579468B2 patent drawing
  • US10579468B2 patent drawing

AI summary

Apparatuses and methods for temperature related error management are described. One or more apparatuses for temperature related error management can include an array of memory cells and a write temperature indicator appended to at least one predetermined number of bytes of the stored data in the array of memory cells. The apparatuses can include a controller configured to determine a numerical temperature difference between the write temperature indicator and a read temperature indicator and determine, from stored operations, an error management operation for the stored data based, at least in part, on comparison of the numerical temperature difference to a temperature difference threshold.