NAND Flash Decoding With Modified LLR for Misplacement Errors

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Solution Overview

Problem

NAND flash memories with two or three bits per cell suffer from program disturb (PD) and single bit cell leakage (SBCL), leading to unreliable data readouts due to misplacement errors, which impair their reliability for certain applications.

Innovation Solution

The implementation of modified Log-Likelihood Ratio (LLR) techniques and constrained coding methods to compensate for PD and SBCL errors, incorporating misplacement probabilities into LLR computations and modifying level patterns to prevent problematic transitions, thereby enhancing the reliability of data readouts in LDPC encoded data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If NAND flash memory uses two or three bits per cell to increase storage capacity, then storage density is improved, but program disturb and single bit cell leakage errors increase, worsening data reliability

Engineering Contradiction:

Improvestorage densityVSAvoiddata reliability

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent modifies the Log-Likelihood Ratio (LLR) computation parameters by incorporating misplacement probabilities into the decoding process. This changes the statistical parameters used in error correction to account for the specific error patterns (program disturb and single bit cell leakage) that occur in multi-bit-per-cell NAND flash memory, thereby improving data reliability while maintaining high storage density

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent introduces an intermediary correction step between reading the raw data and final decoding. The LLR modification process acts as an intermediary that compensates for error effects before the data is fully processed, using probability-based adjustments to mitigate the impact of program disturb and single bit cell leakage errors

Inventive Principle:

Principle #24Intermediary (Mediator)

2Device complexity

If conventional LDPC decoding is used to simplify the decoding process, then device complexity is reduced, but misplacement errors from program disturb and single bit cell leakage are not compensated, worsening decoding accuracy

Engineering Contradiction:

Improvedecoding complexityVSAvoiddecoding accuracy

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The patent modifies the LLR parameters used in LDPC decoding to incorporate misplacement probabilities. This parameter change enhances decoding accuracy by accounting for error patterns without fundamentally changing the LDPC decoding structure, thus maintaining relatively low device complexity while improving measurement precision

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent performs preliminary correction of LLR values before the main LDPC decoding process. By pre-compensating for misplacement errors in the LLR computation stage, the subsequent decoding requires less complex error correction operations, balancing decoding accuracy with acceptable complexity

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS8549380B2Non-volatile memory error mitigation

Publication Date: 2013.10.01 INTEL NDTM US LLC

AI summary

Techniques for decoding levels in non-volatile memory. A level of a cell in a multi-bit non-volatile memory is read. A minimum of Log-Likelihood Ratio (LLR) and a modified LLR to decode the level, wherein the modified LLR is a function of a misplacement probability is used. A value corresponding the decoded level is written to a volatile memory.