NAND Flash Memory Multi-Layer Wiring Architecture
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Solution Overview
Problem
In NAND type flash memory devices, the increasing wire density and miniaturization lead to difficulties in passing cell source lines and cell well lines through the wiring layer, resulting in higher wire resistance and chip size expansion due to the need for wider power supply lines to manage increased capacity and functionality.
Innovation Solution
The solution involves forming cell source lines and cell well lines on a different layer than the bit lines within the cell array region, allowing them to be connected via Vias, and arranging ground drivers outside the cell array to reduce wire resistance and eliminate the need for longer wire connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If cell source lines and cell well lines are arranged in the same layer as bit lines, then wiring density is high and chip area is reduced, but wire resistance increases and manufacturing becomes difficult
Solution Approach 1:
The patent applies dimensionality change by moving cell source lines and cell well lines from the same layer as bit lines to a different layer (upper or lower layer). This vertical separation in the z-dimension allows all wires to coexist without increasing planar density, reducing wire resistance while maintaining compact chip area through multi-layer wiring structure.
2Reliability
If power supply line width is increased to reduce resistance for large capacity memory, then wire resistance decreases, but chip size increases
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension through multi-layer wiring. Power supply lines can be routed on upper or lower layers with sufficient width to reduce resistance, while the planar chip footprint remains compact since the additional wiring space is obtained vertically rather than horizontally.
Solution Approach 2:
The patent segments the wiring into multiple layers, separating bit lines, cell source lines, and cell well lines into different vertical levels. This segmentation allows each wire type to be optimized independently for its specific function without compromising overall chip area efficiency.
3Productivity
If wire pitch is narrowed for high integration, then integration density increases, but it becomes more difficult to pass cell source lines and cell well lines through the wiring layer
Solution Approach 1:
The patent applies dimensionality change by routing cell source lines and cell well lines on different layers from bit lines. This vertical separation provides additional routing space without increasing planar wire pitch, thereby maintaining high integration density while simplifying the manufacturing process by reducing wiring congestion and interference.
Data Source
AI summary
The nonvolatile semiconductor memory device related to an embodiment of the present invention includes a cell array including a memory string, a bit line connected to the memory string, a first wire connected to a cell source line of a memory cell, a second wire connected to a cell well line of a memory cell, a third wire which supplies a power supply voltage to a circuit arranged outside of a region of the cell array, a fourth wire and a fifth wire being arranged in a row direction within the cell array region, and the first wire, the second wire and the third being formed in a layer above a layer in which the bit line within the cell array is formed, the fourth wire and the fifth wire being formed in the layer in which the bit line within the cell array region is formed.