NAND Flash Memory Programming via Multi-Phase Voltage Control
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Solution Overview
Problem
Current programming methods for NAND flash memory devices require numerous incremental step pulse programming (ISPP) cycles, leading to high power consumption due to the need for multiple programming pulses and verify pulses to achieve target threshold voltage levels for data storage.
Innovation Solution
A method involving multi-level programming pulses and verify pulses is introduced, where memory cells are programmed to an interim threshold voltage range before reaching the final target range, using a combination of programming and verify voltage levels to efficiently achieve the desired data states with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If incremental step pulse programming (ISPP) with multiple programming pulses is used to program memory cells, then the memory cells can be reliably programmed to target threshold voltage levels, but the power consumption increases due to the large number of programming pulses and verify pulses required
Solution Approach 1:
The patent segments the programming process into distinct phases with different voltage levels. Instead of using many small incremental pulses, the method divides programming into a first phase with a first voltage level and a second phase with a second voltage level, allowing the system to achieve reliable programming with fewer total pulses by optimizing each phase's contribution to the threshold voltage shift.
Solution Approach 2:
The patent changes the voltage level parameter dynamically during the programming process. By switching between a first voltage level in the first phase and a second voltage level in the second phase, the method optimizes the balance between programming effectiveness and power consumption, reducing the total number of verify pulses needed while maintaining programming reliability.
2Manufacturing precision
If multiple programming pulses are applied to achieve target threshold voltage, then precise control over threshold voltage shifts is possible, but the programming time and number of operations increase
Solution Approach 1:
The patent segments the programming operation into a first phase and a second phase, each with specific voltage levels and termination conditions. This segmentation allows the system to achieve precise threshold voltage control more efficiently by completing portions of the programming task in each phase, reducing the total number of programming-verify cycles needed.
Solution Approach 2:
The first phase of programming acts as a preliminary action that moves memory cells closer to the target threshold voltage before the second phase completes the programming. By performing this preliminary programming with the first voltage level, the system reduces the number of verify pulses needed in subsequent phases, thereby reducing total programming time while maintaining precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of programming-verify phases, lowering power consumption and enhancing the efficiency of data programming in NAND flash memory devices by enabling more precise control over threshold voltage shifts.
Implementation Method 1
a blocking potential is applied to a blocking interface between a channel and a region containing trap states, thereby controlling an energy barrier height at the blocking interface and controlling an amount of carrier injection into the trap states
Data Source
AI summary
Apparatus might include a controller configured to cause the apparatus to program a plurality of memory cells from a first data state to a second data state higher than the first data state, determine a respective first voltage level of a control gate voltage deemed to cause each memory cell of a first and second subset of memory cells of the plurality of memory cells to reach the second data state, determine a respective second voltage level of a control gate voltage deemed sufficient to cause each memory cell of the first subset of memory cells to reach a third data state higher than the second data state, and determine a respective second voltage level of a control gate voltage deemed sufficient to cause each memory cell of the second subset of memory cells to reach a fourth data state higher than the third data state.