Multi-stage Write Sequence for NAND Flash Memory
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Solution Overview
Problem
Current semiconductor memory devices face challenges in write sequence efficiency, particularly in read-intensive SSDs, where write times are longer than read times, leading to potential data reliability issues and increased processing time, especially when write sequences are suspended and resumed.
Innovation Solution
The semiconductor memory device employs a write sequence with multiple stages, including an initial amplitude and incremental program pulses, allowing for a gradual transition of threshold voltage to achieve a fine level in multiple stages, reducing the impact on adjacent cells and minimizing the distribution width, thereby enhancing data reliability and read response speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional write sequence is used with single-stage program pulses, then the write operation can be completed, but the processing time is long and data reliability is reduced due to high-speed threshold drops
Solution Approach 1:
The write sequence is divided into multiple write stages (first write stage, second write stage, third write stage) where each stage applies program pulses with different amplitude characteristics. This segmentation allows gradual threshold voltage transition, reducing high-speed threshold drops and improving data reliability while maintaining efficient write processing.
Solution Approach 2:
The program pulse amplitudes are dynamically adjusted across different write stages. The first write stage uses program pulses with a first amplitude, the second write stage uses program pulses with a second amplitude, and the third write stage uses program pulses with a third amplitude. This dynamic adjustment optimizes the write process to prevent threshold voltage instability while minimizing processing time.
2Productivity
If program pulses with high amplitude are applied to quickly set threshold voltage, then write speed improves, but the impact on adjacent cells increases and distribution width expands
Solution Approach 1:
The program pulses are segmented into multiple groups across different write stages, each with controlled amplitude characteristics. This prevents any single high-amplitude pulse from causing excessive impact on adjacent cells, thereby maintaining narrow threshold distribution width while achieving fast write speeds through the multi-stage process.
Solution Approach 2:
The amplitude parameter of program pulses is changed across different write stages. By transitioning from first amplitude to second amplitude to third amplitude in sequential stages, the system achieves rapid threshold voltage setting without the harmful effects of a single high-amplitude pulse, thus maintaining both write speed and threshold distribution precision.
3Adaptability or versatility
If the write sequence is suspended and resumed to allow read operations, then read-intensive operations are enabled, but data reliability deteriorates due to high-speed threshold drops
Solution Approach 1:
The dynamic multi-stage write sequence with progressively adjusted program pulse amplitudes creates a more stable threshold voltage transition process. This stability reduces high-speed threshold drops that typically occur during suspend-resume operations, enabling reliable data storage even when the write sequence is interrupted for read operations in read-intensive SSD workloads.
Data Source
AI summary
A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells that are NAND-connected; and a control circuit that executes a write sequence, the write sequence writing data to the memory cells, the write sequence including a plurality of write stages, one of the write stages applying to the memory cells a plurality of program pulses whose amplitudes increase by a certain increment, the write stages including 1st to Nth, where N is an integer of 2 or more, write stages, and an initial amplitude and the increment of the program pulse applied in the N−1th write stage being the same as an initial amplitude and the increment of the program pulse applied in the Nth write stage.