NAND Flash Multi-Bit Convolution Using Grouped Memory Cells
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Solution Overview
Problem
Existing neural network operations in NAND flash memory require costly peripheral circuits for multi-bit data convolution, making them unsuitable for mass production.
Innovation Solution
A method for NAND flash memory to perform convolution operations using multiple memory blocks, page buffers, synaptic strings, and word lines, where sub-weight data is written into groups of memory cells, and currents are sensed by page buffers to obtain sub-data, processed to achieve a convolution result.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If NOR memory architecture or ReRAM/PCM memory architecture is used for neural network operation, then the convolution operation can be performed, but a large number of peripheral circuits are needed which increases cost and complexity
Solution Approach 1:
The patent applies universality by making the general NAND flash memory structure perform multiple functions - it serves both as standard storage memory and as the computational array for neural network operations. The memory cells are configured to store weight data while the same structure performs convolution operations through voltage application and current sensing, eliminating the need for separate specialized memory architectures and their associated peripheral circuits.
Solution Approach 2:
The patent extracts the computational function from separate specialized memory architectures and integrates it into the general NAND flash memory structure. By taking out the convolution operation capability and embedding it within the standard memory array, the design eliminates the need for additional peripheral circuits that would be required in NOR or ReRAM architectures.
2Productivity
If specialized memory architecture is used for neural network operation, then the convolution operation can be performed efficiently, but the device is not suitable for mass production
Solution Approach 1:
The patent makes the general NAND flash memory structure universal by enabling it to perform both standard storage operations and neural network convolution operations. This multi-functionality allows the same device structure to be used for both purposes, eliminating the need for specialized memory arrays and their complex peripheral circuits, thereby making it suitable for mass production.
Solution Approach 2:
The patent segments the weight data into sub-weight data and divides the memory cells into groups, where each group stores one piece of sub-weight data. This segmentation allows the convolution operation to be performed by applying voltages to specific groups of memory cells and sensing currents, enabling the general NAND flash memory to perform neural network operations without requiring a completely specialized architecture.
3Device complexity
If general NAND flash memory is used for neural network operation, then the device structure is simple and cost-effective, but the convolution operation of multi-bit data cannot be completed
Solution Approach 1:
The patent segments the multi-bit weight data into sub-weight data and divides the memory cells into groups, where each group stores one piece of sub-weight data. This segmentation enables the general NAND flash memory to perform convolution operations by applying voltages to specific groups and sensing currents, thereby completing the convolution operation of multi-bit data while maintaining a simple and cost-effective memory structure.
Solution Approach 2:
The patent changes the operational parameters of the memory cells by applying target voltages to groups of memory cells and sensing currents to obtain sub-data. This parameter change approach enables the general NAND flash memory to perform convolution operations by manipulating voltage and current parameters, thereby achieving multi-bit data convolution capability without changing the basic memory structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables neural network operation of multi-bit data using general NAND flash memory without the need for costly peripheral circuits, facilitating mass production.
Implementation Method 1
applying a target voltage to the multiple groups of memory cells through the multiple word lines
Implementation Method 2
sensing, by the multiple corresponding page buffers, currents of the memory blocks, so as to obtain multiple pieces of sub-data
Data Source
AI summary
Provided is a method for a NAND flash memory to complete convolution operation of multi-bit data, including the following steps: dividing multiple memory cells connected by the same word line into multiple groups of memory cells, writing sub-weight data into the multiple groups of memory cells according to a corresponding relationship between the sub-weight data and sub-feature data, where one group of memory cells only stores one piece of weight data, and one memory cell in one group of memory cells only stores 1-bit data of the sub-weight data; applying a target voltage to the plurality of groups of memory cells through a plurality of word lines; sensing, by multiple corresponding page buffers, currents of memory blocks to obtain multiple pieces of sub-data; and processing the multiple pieces of sub-data to obtain a convolution result. The neural network operation of multi-bit data is achieved using a general NAND flash memory.