NAND Flash Read Channel With ML Noise Cancellation and ECC
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Solution Overview
Problem
NAND flash memory devices storing multiple bits per cell face challenges with noise susceptibility, leading to performance hindrances in mobile devices due to increased computational power requirements.
Innovation Solution
A memory system incorporating a neural network-based noise cancellation mechanism within a memory controller, which denoises data during read operations using a machine learning core, and employs error correction coding schemes to mitigate interference and improve data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bits are stored per memory cell, then storage density is improved, but noise susceptibility increases
Solution Approach 1:
An interference cancellation component is introduced as an intermediary between the memory cell array and the read channel. This component receives read-disturbed data and actively cancels out interference signals before the data is fully processed, thereby mitigating noise susceptibility while maintaining high storage density
Solution Approach 2:
The system implements feedback mechanisms where read-disturbed data is fed back through the interference cancellation component. The component uses this feedback to identify and subtract interference patterns from subsequent reads, continuously improving signal quality without reducing storage capacity
2Reliability
If noise compensation is performed, then data reliability is improved, but computational power requirement increases
Solution Approach 1:
The interference cancellation component performs noise compensation in advance during the read operation, before the data needs to be fully processed by higher-level computational units. By pre-cancelling interference, the system reduces the computational burden on subsequent error correction and data processing stages
Solution Approach 2:
The system replaces complex computational noise compensation methods with a dedicated interference cancellation hardware component. This substitution shifts the computational workload to specialized circuitry that operates more efficiently with lower power consumption
3Reliability
If interference cancellation is performed, then read reliability is improved, but device complexity increases
Solution Approach 1:
The interference cancellation component is designed to handle multiple types of interference simultaneously (intra-wordline, inter-wordline, and inter-block interference) through a single unified processing path. This multi-functional approach improves read reliability without proportionally increasing device complexity
Data Source
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AI summary
A mobile electronic device may include a memory device (220) and a memory controller (210) including an error correction code (ECC) encoder to encode data, a constrained channel encoder (610) configured to encode an output of the ECC encoder (605) based on one or more constraints, a reinforcement learning pulse programming (RLPP) (610) component configured to identify a programming algorithm for programming the data to the memory device (220), an expectation maximization (EM) signal processing component (635) configured to receive a noisy multi-wordline voltage vector from the memory device (220) and classify each bit of the vector with a log likelihood ration (LLR) value, a constrained channel decoder (640) configured to receive a constrained vector from the EM signal processing component (635) and produce an unconstrained vector, and an ECC decoder (645) configured to decode the unconstrained vector. A machine learning interference cancellation component (650) may operate based on or independent of input from the EM signal processing component (635).