NAND Flash Memory Oblique Word Bit Line Architecture
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Solution Overview
Problem
In NAND flash memory devices, the close proximity of transistors and lines leads to increased interference, causing a wide distribution of threshold voltage and reducing the read window due to parasitic coupling capacitance, which is a significant challenge in manufacturing multi-level cells.
Innovation Solution
The configuration of word lines and bit lines is changed from a perpendicular to an oblique arrangement, staggering the floating gate regions of adjacent memory cells to decrease the overlapping width and coupling capacitance between them, thereby mitigating bit line interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gap between word lines is reduced to increase memory density, then the number of transistors increases, but the space between floating gates is compressed causing increased parasitic coupling capacitance and threshold voltage drift
Solution Approach 1:
The patent applies asymmetry by changing the orthogonal arrangement (90 degrees) to a non-orthogonal arrangement where bit lines and word lines intersect at angles different from 90 degrees. This asymmetric configuration staggers the floating gate regions of adjacent memory cells, reducing their overlapping area and thereby decreasing parasitic coupling capacitance while maintaining high memory density
Solution Approach 2:
The patent introduces a new dimensional parameter by defining the intersection angle between bit lines and word lines as a variable parameter rather than fixing it at 90 degrees. This additional degree of freedom allows optimization of floating gate overlap in the lateral dimension, reducing parasitic capacitance without sacrificing vertical stacking density
2Productivity
If the line width is reduced below 2× nm to increase integration, then transistor size decreases, but bit line direct interference increases and read window reduces
Solution Approach 1:
The non-orthogonal arrangement creates asymmetric spacing between floating gates of adjacent cells along the bit line direction. This asymmetric staggering reduces the direct overlap area between floating gates, thereby decreasing parasitic coupling capacitance and preventing threshold voltage drift that would otherwise reduce the read window in highly integrated structures
Solution Approach 2:
The patent applies local quality by optimizing the spatial relationship between floating gates in specific local regions. By controlling the intersection angle, the floating gate regions are staggered locally to minimize overlap areas where parasitic capacitance would form, while maintaining the overall high integration density of the memory array
3Productivity
If floating gates are positioned closer to increase cell density, then memory capacity increases, but parasitic bit line coupling capacitance increases causing threshold voltage distribution width to increase
Solution Approach 1:
The patent uses asymmetric non-orthogonal arrangement to stagger floating gate positions, creating non-uniform spacing that reduces the overlapping area between adjacent floating gates. This reduces parasitic coupling capacitance and narrows the threshold voltage distribution width, improving manufacturing precision while maintaining high memory capacity
Solution Approach 2:
By introducing the intersection angle as an additional design parameter, the patent optimizes the lateral positioning of floating gates in the bit line direction. This dimensional adjustment staggers floating gate regions to minimize overlap, reducing parasitic capacitance effects and improving threshold voltage control without reducing memory capacity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This oblique configuration reduces the parasitic bit line coupling capacitance, improving the distribution of threshold voltage and enhancing the read window, effectively addressing the interference issues in multi-level cell manufacturing.
Implementation Method 1
a parasitic bit line coupling capacitance C1 is formed therebetween, and the bit line coupling capacitance C1 is a main reason that causes the bit line direct interference
Data Source
AI summary
A memory device including multiple word lines, multiple bit lines and a memory cell array is provided. The word lines intersect the bit lines, and an included angle between the word lines and the bit lines is not a right angle. The memory cell array includes multiple memory cells respectively disposed at the intersections of the word lines and the bit lines. Each row of the memory cells is electrically connected to one of the word lines, and each column of the memory cells is electrically connected to one of the bit lines.