NAND Flash ODT Control via Chip Enable Signals

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Solution Overview

Problem

Existing semiconductor storage devices, such as NAND flash memories, face signal degradation due to signal reflection on data buses, which is not effectively addressed by existing technologies like on-die termination (ODT) since they require additional pins for control, increasing package size and complexity, and costs.

Innovation Solution

Implementing an ODT circuit in each NAND chip that is controlled using chip enable signals and commands, allowing the resistance of the terminating resistor to be set without adding a dedicated pin, thereby inhibiting signal reflection and improving signal characteristics without increasing package size or complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If on-die termination (ODT) is implemented in existing semiconductor storage devices, then signal characteristics are improved, but additional control pins are required which increases package size and complexity

Engineering Contradiction:
Improvesignal characteristicsVSAvoidpackage size and complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The chip enable signal is given dual functionality: it serves both as the traditional chip selection signal and as the control signal for activating the ODT circuit. This eliminates the need for separate control pins while achieving signal termination, directly resolving the contradiction between improving signal characteristics and avoiding increased package complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The control function for ODT is merged with the existing chip enable control mechanism. By combining these functions into a single control path using the same signal lines and control logic, the patent achieves signal termination without adding any external pins or increasing package size

Inventive Principle:
Principle #5Merging (Combining)

2Object-affected harmful factors

If additional control pins are added for ODT, then signal reflection is reduced, but manufacturing costs and package complexity increase

Engineering Contradiction:
Improvesignal reflectionVSAvoidmanufacturing costs
Core Design Contradiction:
Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The chip enable signal performs multiple functions simultaneously: chip selection and ODT control. This multi-functionality eliminates the need for additional control pins, thereby reducing manufacturing costs and package complexity while still achieving the goal of reducing signal reflection

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The ODT circuit is designed to be self-controlled through the existing chip enable signal mechanism. The circuit automatically activates or deactivates based on the chip enable state, eliminating the need for external control infrastructure and reducing manufacturing complexity

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enhances signal characteristics in NAND flash memories by enabling ODT circuits in non-selected chips without adding control pins, reducing signal reflection and standby current, while maintaining a compact package design and reducing costs.

Implementation Method 1

provides a terminating resistor in each semiconductor chip and enables the chip selected for input/output of data and the other terminating resistors of non-selected chips

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS10089257B2Semiconductor storage device and control method thereof
Publication Date: 2018.10.02 KIOXIA CORP
  • US10089257B2 patent drawing
  • US10089257B2 patent drawing
  • US10089257B2 patent drawing

AI summary

According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.