NAND Flash Memory Offset Voltage Compensation for Cycle-Induced Threshold Shifts
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Solution Overview
Problem
As the number of program/erase cycles increases in NAND flash memory devices, the threshold value Vt shifts, leading to deterioration of transconductance (Gm) and potential misreading of memory cells due to reduced current flow, causing data storage issues.
Innovation Solution
A semiconductor memory device and reading method that involves monitoring NAND strings to detect current changes, allowing for the determination and application of offset voltages to read-pass and reading voltages to compensate for threshold value shifts and transconductance deterioration, ensuring accurate data reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of program/erase cycles increases, then the memory cell capacity increases, but the threshold value Vt shifts and transconductance Gm deteriorates causing misreading
Solution Approach 1:
The patent applies preliminary action by detecting the current flowing through the monitoring NAND string before the actual read operation, and determining the offset voltage in advance. This allows the system to compensate for threshold value shifts and transconductance deterioration before they cause misreading, thereby maintaining data reading accuracy throughout the program/erase cycle life.
Solution Approach 2:
The patent implements feedback by continuously monitoring the current through the monitoring NAND string and using this information to adjust the offset voltage for subsequent read operations. The detected current reflects the degree of threshold value shift and transconductance deterioration, and this feedback is used to dynamically adjust the reading voltage to compensate for these changes.
2Speed
If reading voltage is optimized for fresh memory cells, then read speed is maximized, but memory cells with many program/erase cycles are misread due to threshold value shift
Solution Approach 1:
The patent applies dynamics by making the reading voltage dynamic rather than fixed. The offset voltage is adjusted based on the detected current from the monitoring NAND string, which reflects the program/erase cycle history. This allows the reading voltage to adapt to the actual state of the memory cells, maintaining both read speed and accuracy across different cycle counts.
3Measurement precision
If monitoring NAND string is added to track program/erase cycles, then threshold value shift can be compensated, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the monitoring NAND string to serve multiple functions: it monitors the program/erase cycle history, provides a reference for threshold value shift detection, and enables offset voltage determination. This multi-functional approach allows accurate measurement of cycle effects without proportionally increasing device complexity.
Data Source
AI summary
A flash memory including a NAND memory cell array, a current detection unit, an offset voltage determining unit, and a reading voltage generating unit. The NAND memory cell array forms at least one monitoring NAND string in each block, which are used to monitor the cycle frequency of programing and erasing. The current detection unit detects the current that flows through the monitoring NAND string. The offset voltage determining unit determines the first offset voltage and the second offset voltage that are respectively added to the read-pass voltage and the reading voltage, according to the current detected. The reading voltage generating unit generates the read-pass voltage with the first offset voltage added. The reading voltage generating unit also generates the reading voltage with the second offset voltage added.