NAND Flash Memory Offset Voltage Compensation for FG Coupling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In NAND flash memory, the threshold value fluctuations due to Floating Gate (FG) coupling with adjacent memory cells lead to unstable read operations and incorrect data retrieval, especially when programming in ascending order, causing the memory cell in the erased state to be mistakenly determined as programmed.
Innovation Solution
A method involving a monitoring NAND string per block, where the programming device programs memory cells connected to the selected word line and detects the programmed state of the unselected word line, allowing for the determination and application of offset voltages to the reading pass and read voltages to compensate for threshold value fluctuations, ensuring accurate data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are highly integrated to increase storage capacity, then productivity and storage density are improved, but Floating Gate coupling effects between adjacent memory cells cause threshold value fluctuations that worsen read operation stability and data accuracy
Solution Approach 1:
The patent applies preliminary action by detecting the programmed state of the unselected word line n+1 before performing the read operation on the selected word line n. Based on this advance detection, the system pre-adjusts the read voltage and reading pass voltage to compensate for anticipated threshold value fluctuations caused by Floating Gate coupling, thereby ensuring stable and accurate read operations in highly integrated memory structures.
2Productivity
If the unselected word line n+1 is programmed, then storage capacity is improved, but the threshold value of the selected memory cell n increases due to FG coupling, causing read margin reduction and potential read errors
Solution Approach 1:
The patent implements feedback by detecting the programmed state of the unselected word line n+1 and using this information to dynamically adjust the read voltage and reading pass voltage applied to the selected word line n. This feedback mechanism compensates for threshold value fluctuations caused by Floating Gate coupling, maintaining adequate read margin and preventing read errors even when adjacent memory cells are programmed.
3Measurement precision
If offset voltages are added to reading pass voltage and read voltage to compensate for threshold fluctuations, then read accuracy is improved, but device complexity increases due to additional voltage control circuitry
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the voltage parameters (read voltage and reading pass voltage) based on the detected state of the unselected word line. By changing these voltage parameters in response to Floating Gate coupling effects, the system compensates for threshold value fluctuations and maintains high read accuracy without requiring complex additional hardware structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively compensates for threshold value fluctuations, ensuring accurate data reading by adjusting voltages based on the detected programmed state of adjacent memory cells, thereby enhancing the reliability of NAND flash memory operations.
Implementation Method 1
the effects of FG (Floating Gate) coupling between memory cells cannot be ignored. For example, when data '0' is programmed into the memory cell Ma of an even page, and as the threshold value of the memory cell Ma rises, the threshold value of the memory cell Mb of the odd page adjacent to the memory cell Ma rises due to the FG coupling with the memory cell Ma.
Data Source
AI summary
A semiconductor device that can compensate for threshold fluctuations in memory cells using capacitive coupling. The flash memory includes a NAND-type memory cell array, a programing device, a reading device, and an offset voltage determining unit. The programing device programs the memory cells connected to a selected word line. The reading device reads the memory cells connected to a selected word line. The programing device programs the memory cells of a monitoring NAND string simultaneously when programing a word line. The reading device comprises a current detecting unit applying a read voltage to an unselected word line n+1, and detecting the current of the monitoring NAND string. The offset voltage determining unit determines the first and second offset voltage based on the detected current, and a reading pass voltage is applied to the unselected word line, a read voltage is applied to the selected word line.