NAND Flash Memory Over-Programming Read Voltage Adaptation

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Solution Overview

Problem

NAND flash memory devices face issues with over-programming failures, where a memory cell becomes unable to turn on, leading to the inability to read data from affected NAND strings, resulting in defective blocks due to excessive writing and erroneous writing determinations.

Innovation Solution

A nonvolatile semiconductor memory device with a controller that applies a higher read voltage to unselected word lines in blocks with over-programming failures, allowing data to be read from memory cells that were previously inaccessible due to over-programming, and uses a flag system to verify and manage over-programming occurrences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a normal read voltage is applied to unselected word lines, then read disturbance is minimized, but data cannot be read from blocks with over-programming failures

Engineering Contradiction:
Improvedata readabilityVSAvoidread disturbance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies different read voltages to different blocks based on their over-programming status. Blocks identified as having over-programming failures receive a higher read voltage, while normal blocks continue to use the standard read voltage. This localized adaptation resolves the contradiction by tailoring the voltage level to the specific condition of each block, enabling data retrieval from affected blocks without unnecessarily increasing read disturbance across all blocks.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent dynamically changes the read voltage parameter based on the detected over-programming status of memory blocks. When over-programming is detected in a block, the read voltage for that specific block is increased from the normal level to a higher level that can overcome the threshold voltage shifts caused by over-programming. This parameter adaptation allows the system to maintain data readability in affected blocks while keeping the voltage level (and thus read disturbance) at normal levels for unaffected blocks.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a higher read voltage is applied to all blocks, then data can be read from blocks with over-programming failures, but read disturbance increases in normal blocks

Engineering Contradiction:
Improvedata readabilityVSAvoidread disturbance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent implements selective voltage application where only blocks with detected over-programming failures receive the higher read voltage. The controller identifies affected blocks and applies the elevated voltage exclusively to those blocks during read operations, while normal blocks continue to use the standard read voltage. This localized approach resolves the contradiction by concentrating the higher voltage effect only where needed, thereby maintaining data readability in affected blocks without unnecessarily increasing read disturbance in normal blocks.

Inventive Principle:
Principle #3Local quality

3Reliability

If over-programming verification is performed, then defective blocks can be identified, but additional write cycles are required

Engineering Contradiction:
Improvedefect detection accuracyVSAvoidwrite operation speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent performs over-programming verification immediately after the write operation completes, before the memory block is made available for subsequent operations. By conducting this verification in advance, the system identifies blocks with over-programming failures early in the process flow, allowing these blocks to be flagged and handled differently in future read operations. This preliminary detection resolves the contradiction by catching defects at the earliest opportunity, ensuring high detection accuracy without requiring additional dedicated verification cycles later.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8891304B2Nonvolatile semiconductor memory device and memory system
Publication Date: 2014.11.18 KIOXIA CORP
  • US8891304B2 patent drawing
  • US8891304B2 patent drawing
  • US8891304B2 patent drawing

AI summary

According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array includes blocks, each of the blocks includes NAND strings that each comprise memory cells serially connected in a first direction, word lines respectively connected to memory cell groups arranged in a second direction in the block, and a controller configured to perform a process (A) of verifying one of states in which all of the memory cells included in the block are turned on (pass) and at least one memory cell is turned off (fail) by use of a first read voltage applied to unselected word lines in a data read time, and to perform a process (B) of reading data from the fail block by use of a second read voltage that is higher than the first read voltage and applied to the unselected word lines.