Serial NAND Flash Memory Page Boundary Read Continuity

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Solution Overview

Problem

High-density serial NAND flash memory lacks the cost advantage of serial NOR flash memory while facing architectural, performance, and bad block limitations, making it unsuitable for high-speed code shadowing applications, and it is not compatible with serial NOR flash memory controllers.

Innovation Solution

A high-performance serial NAND flash memory device with a compact package and active SPI interface, incorporating a page buffer and control logic to enable continuous data output across page boundaries without wait intervals, compatible with serial NOR flash memory read commands and controllers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If high-density serial NAND flash memory is used, then storage capacity is improved, but cost advantage is lost and performance limitations occur

Engineering Contradiction:

Improvestorage capacityVSAvoidperformance reliability

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the NAND flash memory operation into two distinct modes: standard NAND mode for general storage and High Performance Serial Flash (HPSF) mode for code shadowing applications. This segmentation allows the same physical memory device to serve different functional requirements, maintaining cost advantages while achieving NOR-like performance when needed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic mode switching capability that allows the memory device to transition between standard NAND operation and HPSF mode based on application requirements. The controller can dynamically select operating modes, enabling the system to optimize between cost and performance depending on the specific task being performed.

Inventive Principle:

Principle #15Dynamics

2Ease of manufacture

If standard NAND flash memory is used, then cost advantage is maintained, but code shadowing performance is insufficient

Engineering Contradiction:

Improvecost advantageVSAvoidcode shadowing speed

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The patent changes key operational parameters when switching to HPSF mode, including disabling bad block management and ECC processing during code shadowing operations, and enabling continuous read across page boundaries. These parameter changes eliminate the performance bottlenecks present in standard NAND operation while maintaining the same physical device, thereby achieving NOR-like code shadowing speeds without increasing manufacturing cost.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

Inventive Principle:

Principle #15Dynamics

3Productivity

If continuous read across page boundaries is enabled, then code shadowing performance is improved, but architectural complexity increases

Engineering Contradiction:

Improvecode shadowing speedVSAvoidarchitectural complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a buffer memory as an intermediary component that stores data from the NAND flash memory array. This buffer allows continuous read operations across page boundaries by holding data that spans multiple pages, eliminating the need for complex real-time page boundary management during code shadowing operations and simplifying the overall architecture.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Adaptability or versatility

If serial NOR flash memory is used for code shadowing, then compatibility with NOR controllers is achieved, but cost advantage is lost at high densities

Engineering Contradiction:

Improvecontroller compatibilityVSAvoidcost per bit

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent makes the NAND flash memory device universal by enabling it to function in both standard NAND modes and HPSF mode that is compatible with serial NOR flash controllers. The device can serve as either NAND or NOR flash depending on the operating mode, allowing systems to use a single memory type for multiple applications and eliminating the need for separate NOR flash devices in code shadowing applications.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10068654B2NAND flash memory

Publication Date: 2018.09.04 WINBOND ELECTRONICS CORP

AI summary

Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.