NAND Flash Page Buffer for AES Encryption Circuit Downsizing
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Solution Overview
Problem
Current AES circuit designs for nonvolatile semiconductor storage devices are large due to the need for external RAM to operate encryption processes, and there is a lack of studies on downsizing these circuits when they are integrated into other systems rather than standalone devices.
Innovation Solution
The integration of a NAND flash memory as the AES key storage device and a page buffer as RAM within the NAND chip, allowing the AES encrypting circuit to operate within the NAND chip's peripheral area, eliminating the need for external storage and reducing circuit size by utilizing the page buffer for both key storage and arithmetic operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If external RAM is used for AES encryption operations, then the encryption function can be implemented, but the overall circuit size increases
Solution Approach 1:
The patent merges the AES encryption circuit with the NAND flash memory chip by utilizing the page buffer as RAM for encryption operations. This integration eliminates the need for separate external RAM, reducing overall circuit size while maintaining full AES encryption functionality through the combined hardware resources within the chip.
Solution Approach 2:
The page buffer is designed to serve multiple functions: it acts as both the data buffer for NAND flash operations and as the RAM memory for AES encryption calculations. This multi-functionality allows the system to implement encryption without requiring dedicated separate memory resources, thereby reducing circuit complexity.
2Device complexity
If the page buffer is used as RAM for AES operations, then the circuit size is reduced, but error detection capability may be compromised
Solution Approach 1:
The patent segments the page buffer into distinct functional regions: a first region for storing data read from the memory cell array and a second region for AES encryption operations. This segmentation allows the same physical buffer to serve different purposes with clear data flow separation, maintaining reliability through structured data management while achieving circuit size reduction.
Solution Approach 2:
The inspection circuit provides feedback about data errors to the control circuit, which then determines whether to supply data from the first region to the second region or to re-read data from the memory cell array. This feedback mechanism ensures that only error-free data is used for encryption operations, maintaining reliability despite the shared buffer usage.
3Reliability
If inspection circuit is added for error checking, then data reliability is improved, but device complexity increases
Solution Approach 1:
The inspection circuit is integrated within the existing page buffer structure, allowing the system to self-check data integrity without requiring external assistance. The control circuit automatically manages the inspection process, determining when data needs to be re-read based on inspection results, thereby improving reliability while minimizing additional complexity through self-contained error checking.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor storage device includes an encrypting circuit for operating in a predetermined encrypting system, a memory cell array preliminarily storing complementary data to be used in the operation, and a page buffer having a first region for storing the data being read out from the memory cell array, and a second region used when executing the operation.