NAND Flash Memory Page Buffer as External Data Cache
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Solution Overview
Problem
Conventional semiconductor devices with integrated NAND flash memory and ECC (Error Checking and Correcting) function require additional circuit area for SRAM data buffers, increasing the overall circuit size due to the need for data buffers during data transfer operations.
Innovation Solution
A semiconductor device configuration that integrates a NAND flash memory, an input/output unit with ECC functionality, and a data bus switch, allowing the page buffer within the NAND flash memory to function as both a primary and secondary cache, eliminating the need for external SRAM buffers by parallel connection of ECC and user data buses, thereby reducing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SRAM data buffers are added to enable parallel data transfer between NAND flash memory and external apparatus, then data throughput is improved, but circuit area increases
Solution Approach 1:
The patent merges the NAND flash memory's internal page buffer with the external data buffer functionality by directly connecting the page buffer to the external apparatus interface. This eliminates the need for separate SRAM buffers while maintaining the ability to perform parallel data transfer, thereby improving data throughput without increasing circuit area.
Solution Approach 2:
The page buffer within the NAND flash memory is made to serve dual functions: its traditional role in temporary data storage during write operations, and additionally as an external data buffer for parallel data transfer. This multi-functionality approach allows the system to achieve high data throughput without adding dedicated SRAM buffer circuits.
2Productivity
If two SRAM data buffers are used to increase data throughput, then productivity is improved, but device complexity increases
Solution Approach 1:
Instead of implementing two separate SRAM data buffers, the patent combines the functionality of both buffers into the existing page buffer structure of the NAND flash memory. This merging approach maintains high data throughput capability while significantly reducing device complexity by eliminating redundant buffer circuits and their associated control logic.
Solution Approach 2:
The patent extracts the essential buffer functionality from the traditional SRAM buffer design and integrates it directly into the NAND flash memory's page buffer. This extraction eliminates the need for separate external SRAM buffers and simplifies the overall device architecture while preserving the parallel data transfer capability.
3Productivity
If SRAM buffers are integrated into the semiconductor device, then data transfer capability is improved, but manufacturing cost increases due to additional circuit area
Solution Approach 1:
The patent merges the data buffer functionality with the existing page buffer circuitry of the NAND flash memory, eliminating the need for separate SRAM buffer circuits. This reduces the total circuit area that needs to be manufactured, thereby lowering manufacturing costs while maintaining improved data transfer capability.
Solution Approach 2:
By making the page buffer multi-functional (serving both as internal buffer and external data buffer), the patent avoids the need to manufacture additional dedicated SRAM buffer circuits. This universal approach reduces manufacturing complexity and cost while achieving enhanced data transfer performance.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a NAND flash memory, an input/output unit, a switch, and a controller. The input/output unit includes an ECC unit configured to perform an ECC process on data input to the NAND flash memory, and/or data output from the NAND flash memory, and an interface configured to exchange data with an external apparatus, and controls input/output of data between the NAND flash memory and the external apparatus. The switch is connected to the NAND flash memory and the input/output unit. The controller controls the NAND flash memory and the input/output unit, and switches a connection between the NAND flash memory and the ECC unit, and a connection between the NAND flash memory and the interface via the switch.