NAND Flash Page Buffer Exclusion Circuit Programming
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Solution Overview
Problem
Traditional multi-level-cell NAND flash memory devices face challenges in reducing programming time due to the complexity of programming states and the need for multiple memory cells, leading to inefficiencies in programming operations.
Innovation Solution
A method for programming multi-level-cell NAND flash memory devices that utilizes a limited-program approach in Phase One, combined with an exclusion circuit in a page buffer, to efficiently program memory cells to specific states, reducing programming time by controlling the programming of each bit of two-bit data through a series of signal activations and verifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional multi-level-cell NAND flash memory devices use multiple memory cells to store 2-bit information, then data storage capacity is improved, but programming time increases due to the complexity of programming states
Solution Approach 1:
The programming operation is divided into multiple phases (Phase One, Phase Two, Phase Three) with distinct objectives. Phase One programs memory cells to first state (10) or second state (00), Phase Two programs to third state (01), and Phase Three verifies and completes programming. This segmentation allows parallel programming of different states simultaneously, reducing total programming time while maintaining 2-bit storage capacity per cell.
Solution Approach 2:
Before the main programming operation, memory cells are pre-programmed to the first state (10) using a limited-program approach in Phase One. This preliminary action establishes a baseline state that enables subsequent programming operations to proceed more efficiently. The exclusion circuit is also activated in advance to control which memory cells receive programming signals, preventing unnecessary programming operations and reducing overall programming time.
2Reliability
If traditional programming methods program memory cells sequentially through multiple phases, then programming completeness is ensured, but programming time cannot be reduced
Solution Approach 1:
In Phase One, memory cells are pre-programmed to the first state (10) using a limited-program approach. This preliminary programming action prepares the memory cells for subsequent operations, ensuring that when Phase Two and Phase Three execute, the cells are already in the correct intermediate states. This reduces the time needed for complete programming while maintaining reliability through the multi-phase verification process.
Solution Approach 2:
The programming operation maintains continuous useful action by overlapping multiple programming phases. While Phase One programs cells to state (10) or (00), Phase Two simultaneously programs cells to state (01), and Phase Three verifies and completes the programming. This continuous, overlapping execution ensures that programming operations are always progressing without idle time, maximizing programming speed while ensuring completeness through the exclusion circuit's coordinated control.
3Loss of time
If an exclusion circuit is introduced to control programming of each bit of two-bit data, then programming time is reduced, but device complexity increases
Solution Approach 1:
The exclusion circuit acts as an intermediary component between the control logic and the memory cells. It receives control signals and uses them to selectively enable or disable programming operations for specific memory cells. By placing this intermediary circuit in the page buffer, the complexity is centralized in a dedicated component rather than distributed throughout the entire memory array, making the added complexity manageable and localized.
Data Source
AI summary
A method for programming a multi-level-cell NAND flash memory device having plural memory cells is disclosed to reduce the programming time. The method comprises: programming each memory cell to a zero state, programming from the zero state to a first state by activating a first program signal and programming from the zero state to a quasi-second state and a semi-third state by activating a second program signal, programming from the quasi-second state to a second state and programming from the semi-third state to a quasi-third state by activating the second program signal, and programming from the quasi-third state to a third state by activating the first program signal. The present invention also discloses a page buffer to perform the method for programming a multi-level-cell NAND flash memory device, which comprises a bit line selection circuit, a first register, a second register, a first verify circuit, a second verify circuit and an exclusion circuit.