NAND Flash Page Buffer Latch Noise Reduction via Segmented Activation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional NAND flash memory devices experience power supply voltage drops due to rapid current increases, leading to latch noise caused by charge sharing between internal nodes, which can result in data value inversion during page buffer operations.
Innovation Solution
The page buffer is configured with a latch connected to a sense node at a first contact point and a sensing circuit at a second contact point, with a switch circuit that electrically connects the two points after the first point is charged, allowing for sequential activation of latches and reducing voltage fluctuations by maintaining a capacitance ratio between load capacitance elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If all latches in the page buffer circuit are activated simultaneously, then data storage capacity is maximized, but current flowing along the data path increases rapidly causing power supply voltage drop
Solution Approach 1:
The page buffer circuit is divided into multiple groups of latches (first group, second group, third group) that are activated sequentially rather than simultaneously. Each group is activated in a predetermined sequence with time intervals between activations, which segments the total current demand into smaller pulses over time, preventing the rapid current increase that would cause power supply voltage drop while still achieving full data storage capacity.
2Power
If latches are activated sequentially in groups, then power supply voltage drop is reduced, but voltage applied to latch node may drop below trip point due to charge sharing between internal nodes
Solution Approach 1:
Before activating a latch group, the circuit maintains appropriate voltage levels on internal nodes by controlling the timing sequence. The predetermined time intervals between group activations allow voltage to stabilize and prevent charge sharing effects that would cause voltage to drop below the trip point. This preliminary voltage preparation ensures reliable latch operation while maintaining power stability.
Solution Approach 2:
The control logic block monitors and adjusts the activation timing of different latch groups based on the overall system state. This feedback mechanism ensures that voltage levels remain within safe operating ranges during sequential latch activation, preventing charge sharing induced voltage drops below trip points while maintaining both power stability and data integrity.
3Speed
If page buffers are activated in rapid succession, then operation speed is improved, but latch noise increases due to voltage fluctuations
Solution Approach 1:
Latch groups are activated in a periodic sequence with predetermined time intervals between activations. This periodic action pattern allows voltage to settle between successive latch activations, reducing voltage fluctuations and latch noise while maintaining high operation speed. The regular timing rhythm prevents cumulative noise buildup that would occur with random or simultaneous activation patterns.
Data Source
AI summary
A page buffer may comprise of a latch connected to a sense node at a first contact point. The page buffer may also comprise of a sensing circuit connected to the sense node at a second contact point, the sensing circuit being configured to sense cell data of the sense node. The page buffer may also comprise of a switch circuit which electrically connects the first contact point with the second contact point after the first contact point is charged by the latch.