NAND Flash Memory Page Buffer Precharge Overlap
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Solution Overview
Problem
Existing memory devices face challenges in minimizing bit line precharge time during program verify operations, which affects the efficiency of checking the program state and operation in NAND flash memory systems.
Innovation Solution
The proposed solution involves a memory device with page buffers connected to memory cells through bit lines, and a control circuit that performs a first verify operation by precharging at least one bit line and applying a verify voltage to the selected word line, followed by a second verify operation with different bit line precharge and verify voltage settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential verify operations are performed on different bit line groups, then program state checking is achieved, but bit line precharge time increases
Solution Approach 1:
The patent applies preliminary action by precharging the first bit line group before the second verify operation begins. The control circuit precharges the first bit line group to a first precharge voltage level in advance, then maintains or adjusts this precharge level during the second verify operation based on sensed threshold voltage values. This eliminates the need to wait for the first bit line group to be precharged after the second verify operation starts, thereby overlapping operations and reducing total precharge time.
Solution Approach 2:
The patent employs dynamics by making the precharge voltage level of the first bit line group adjustable and conditional. Rather than using a fixed precharge sequence, the control circuit dynamically adjusts the precharge voltage level of the first bit line group during the second verify operation based on the sensed threshold voltage values. This dynamic adjustment allows the system to optimize performance by adapting precharge behavior to actual memory cell states, reducing unnecessary waiting time while ensuring accurate verification.
2Reliability
If multiple bit line groups are precharged separately, then verify operation accuracy is maintained, but current consumption increases
Solution Approach 1:
The patent applies local quality by differentiating the treatment of different bit line groups based on their operational status and requirements. The control circuit senses threshold voltage values from memory cells connected to the first bit line group during the second verify operation, and based on these sensed values, selectively adjusts the precharge voltage level of only the first bit line group. This localized, conditional precharge approach ensures verify accuracy for each bit line group while avoiding unnecessary current consumption from uniformly precharging all bit lines regardless of need.
Data Source
AI summary
A memory device includes: a plurality of page buffers connected a plurality of bit lines and configured to selectively precharge the bit lines, and a control circuit configured to: perform a first verify operation by applying a precharge voltage to a first bit line among the bit lines according to program data and by applying a first verify voltage to a selected word line, perform a second verify operation, after the first verify operation, by applying the precharge voltage to a second bit line not overlapping the first bit line and by applying a second verify voltage to the selected word line, and perform at least one of an operation of floating the first bit line and an operation of applying the precharge voltage according to a threshold voltage of a memory cell connected to the first bit line during the second verify operation.